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AM3703CUS Datasheet(PDF) 260 Page - Texas Instruments |
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AM3703CUS Datasheet(HTML) 260 Page - Texas Instruments |
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260 / 280 page ![]() SWPS038-097 mmcx_clk mmcx_cmd mmcx_dat[n:0] HSSD5 HSSD5 HSSD6 HSSD6 HSSD1 HSSD2 HSSD2 AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com Figure 6-74. MMC2 and MMC3 Interfaces —High-Speed SDIO Mode—Data/Command Transmit(1) (1) In mmcx, x = 2 or 3. In mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3. 6.6.8.1.8 MMC2 and MMC3 Interfaces —Standard SDIO Mode Table 6-131 and Table 6-132 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-89 and Figure 5-90). Table 6-130. MMC2 and MMC3 Interfaces Timing Conditions —Standard SDIO Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 10 ns tF Input signal fall time 10 ns Output Condition CLOAD Output load capacitance(1) 5 pF (1) Buffer strength configuration: SPEEDCTRL = 1 Table 6-131. MMC2 and MMC3 Interfaces Timing Requirements —Standard SDIO Mode(2)(3) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC2 and MMC3 Interface (1.8-V IO) SD3 tsu(CMDV-CLKIH) Setup time, mmcx_cmd valid before 3.3 21.9 ns mmcx_clk rising clock edge SD4 th(CLKIH-CMDIV) Hold time, mmcx_cmd valid after mmcx_clk 18.1 36.7 ns rising clock edge SD7 tsu(DATxV-CLKIH) Setup time, mmcx_dat[n:0](1) valid before 3.3 21.9 ns mmcx_clk rising clock edge SD8 th(CLKIH-DATxIV) Hold time, mmcx_dat[n:0](1) valid after 18.1 36.7 ns mmcx_clk rising clock edge (1) In mmcx_dat[n:0], n is equal to 3 for MMC2 and 7 for MMC3. (2) See Section 4.3.4, Processor Clocks. (3) In mmcx, x is equal to 2 or 3. Table 6-132. MMC2 and MMC3 Interfaces Switching Characteristics —Standard SDIO Mode(6)(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX Standard SDIO Mode SD1 tc(clk) Frequency(1), output clock period 24 12 MHz SD2 tW(clkH) Typical pulse duration, output clock high X(4) * X(4) * ns PO(2) PO(2) SD2 tW(clkL) Typical pulse duration, output clock low Y(5) * Y(5) * ns PO(2) PO(2) tdc(clk) Duty cycle error, output clock 2083.33 4166.67 ps 260 Timing Requirements and Switching Characteristics Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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