EP3C80 datasheet(103/274 Pages) ALTERA

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Chapter 6: I/O Features in the Cyclone III Device Family

6–5

I/O Element Features

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Programmable Pull-Up Resistor

Each Cyclone III device family I/O pin provides an optional programmable pull-up

resistor while in user mode. If you enable this feature for an I/O pin, the pull-up

resistor holds the output to the VCCIO level of the output pin’s bank.

1 If you enable the programmable pull-up, the device cannot use the bus-hold feature.

Programmable pull-up resistors are not supported on the dedicated configuration,

JTAG, and dedicated clock pins.

1 When the optional DEV_OE signal drives low, all I/O pins remain tri-stated even if the

programmable pull-up option is enabled.

Programmable Delay

The Cyclone III device family IOE includes programmable delays to ensure zero hold

times, minimize setup times, increase clock-to-output times, or delay the clock input

signal.

A path in which a pin directly drives a register may require a programmable delay to

ensure zero hold time, whereas a path in which a pin drives a register through

combinational logic may not require the delay. Programmable delays minimize setup

time. The Quartus II Compiler can program these delays to automatically minimize

setup time while providing a zero hold time. Programmable delays can increase the

provides a programmable delay to the global clock networks.

Table 6–2 lists the programmable delays for the Cyclone III device family.

There are two paths in the IOE for an input to reach the logic array. Each of the two

paths can have a different delay. This allows you to adjust delays from the pin to the

internal logic element (LE) registers that reside in two different areas of the device.

You must set the two combinational input delays with the input delay from pin to

internal cells logic option in the Quartus II software for each path. If the pin uses the

input register, one of the delays is disregarded and the delay is set with the input

delay from pin to input register logic option in the Quartus II software.

The IOE registers in each I/O block share the same source for the preset or clear

features. You can program preset or clear for each individual IOE, but you cannot use

both features simultaneously. You can also program the registers to power-up high or

low after configuration is complete. If programmed to power-up low, an

asynchronous clear can control the registers. If programmed to power-up high, an

Table 6–2. Cyclone III Device Family Programmable Delay Chain

Programmable Delays

Quartus II Logic Option

Input pin-to-logic array delay

Input delay from pin to internal cells

Input pin-to-input register delay

Input delay from pin to input register

Output pin delay

Delay from output register to output pin

Dual-purpose clock input pin

delay

Input delay from dual-purpose clock pin to fan-out destinations

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