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CIII51007-3.4

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Cyclone III Device Handbook

Volume 1

July 2012

ISO

9001:2008

Registered

6. I/O Features in the Cyclone III

Device Family

This chapter describes the I/O features offered in the Cyclone® III device family

(Cyclone III and Cyclone III LS devices).

The I/O capabilities of the Cyclone III device family are driven by the diversification

of I/O standards in many low-cost applications, and the significant increase in

required I/O performance. Altera’s objective is to create a device that accommodates

your key board design needs with ease and flexibility.

The I/O flexibility of the Cyclone III device family is increased from the previous

generation low-cost FPGAs by allowing all I/O standards to be selected on all I/O

banks. Improvements to on-chip termination (OCT) support and the addition of true

differential buffers have eliminated the need for external resistors in many

applications, such as display system interfaces. Altera’s Quartus® II software

completes the solution with powerful pin planning features that allow you to plan

and optimize I/O system designs even before the design files are available.

This chapter contains the following sections:

■

“Cyclone III Device Family I/O Elements” on page 6–1

■

“I/O Element Features” on page 6–2

■

“OCT Support” on page 6–7

■

“I/O Standards” on page 6–11

■

“Termination Scheme for I/O Standards” on page 6–13

■

“I/O Banks” on page 6–16

■

“Pad Placement and DC Guidelines” on page 6–21

Cyclone III Device Family I/O Elements

Cyclone III device family I/O elements (IOEs) contain a bidirectional I/O buffer and

five registers for registering input, output, output-enable signals, and complete

embedded bidirectional single-data rate transfer. I/O pins support various

single-ended and differential I/O standards.

The IOE contains one input register, two output registers, and two output-enable (OE)

registers. The two output registers and two OE registers are used for DDR

applications. You can use input registers for fast setup times and output registers for

fast clock-to-output times. Additionally, you can use OE registers for fast

clock-to-output enable timing. You can use IOEs for input, output, or bidirectional

data paths.

July 2012

CIII51007-3.4

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