EP3C80 datasheet(183/274 Pages) ALTERA

183 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–25

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Single-Device AP Configuration

The following groups of interface pins are supported in Micron P30 and P33 flash

memories:

■

Control pins

■

Address pins

■

Data pins

Following are the control signals from the supported parallel flash memories:

■ CLK

■

active-low reset (RST#)

■

active-low chip enable (CE#)

■

active-low output enable (OE#)

■

active-low address valid (ADV#)

■

active-low write enable (WE#)

The supported parallel flash memories output a control signal (WAIT) to Cyclone III

devices to indicate when synchronous data is ready on the data bus. Cyclone III

devices have a 24-bit address bus connecting to the address bus (A[24:1]) of the flash

memory. A 16-bit bidirectional data bus (DATA[15..0]) provides data transfer between

the Cyclone III device and the flash memory.

The following are the control signals from the Cyclone III device to flash memory:

■

DCLK

■

nRESET

■

FLASH_nCE

■

nOE

■

nAVD

■

nWE

EP3C80 Datasheet(PDF) 183 Page - Altera Corporation

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