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EP3C80 Datasheet(PDF) 205 Page - Altera Corporation |
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EP3C80 Datasheet(HTML) 205 Page - Altera Corporation |
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205 / 274 page  Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family 9–47 Configuration Features August 2012 Altera Corporation Cyclone III Device Handbook Volume 1 FPP Configuration Timing Figure 9–23 shows the timing waveform for FPP configuration when using an external host. Table 9–14 lists the FPP configuration timing parameters for Cyclone III device family. Figure 9–23. FPP Configuration Timing Waveform (1) Notes to Figure 9–23: (1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (2) After power-up, the Cyclone III device family holds nSTATUS low during POR delay. (3) After power-up, before and during configuration, CONF_DONE is low. (4) Do not leave DCLK floating after configuration. It must be driven high or low, whichever is more convenient. (5) DATA[7..0] is available as user I/O pin after configuration; the state of the pin depends on the dual-purpose pin settings. nCONFIG nSTATUS (2) CONF_DONE (3) DCLK DATA[7..0] User I/O INIT_DONE Byte 0 Byte 1 Byte 2 Byte 3 Byte n-1 tCD2UM tCF2ST1 tCF2CD tCFG tCH tCL tDH tDSU tCF2CK tSTATUS tCLK tCF2ST0 tST2CK User Mode (5) Tri-stated with internal pull-up resistor (4) User Mode Byte n Table 9–14. FPP Timing Parameters for Cyclone III Device Family (Part 1 of 2) Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 500 ns tCF2ST0 nCONFIG low to nSTATUS low — 500 ns tCFG nCONFIG low pulse width 500 — ns tSTATUS nSTATUS low pulse width 45 230 (1) s tCF2ST1 nCONFIG high to nSTATUS high — 230 (1) s tCF2CK nCONFIG high to first rising edge on DCLK 230 (1) — s tST2CK nSTATUS high to first rising edge of DCLK 2— s tDSU DATA setup time before rising edge on DCLK 5— ns tDH DATA hold time after rising edge on DCLK 0— ns tCH DCLK high time 3.2 — ns tCL DCLK low time 3.2 — ns tCLK DCLK period 7.5 — ns fMAX DCLK frequency — 100 (3) MHz tCD2UM CONF_DONE high to user mode (2) 300 650 s |
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