EP3C80 datasheet(210/274 Pages) ALTERA

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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

Configuration Features

Cyclone III Device Handbook

August 2012

Altera Corporation

Volume 1

Cyclone III device family has dedicated JTAG pins that function as JTAG pins. You

can perform JTAG testing on Cyclone III device family before, during, and after

configuration. Cyclone III device family supports the BYPASS, IDCODE, and SAMPLE

instructions during configuration without interrupting configuration. All other JTAG

instructions can only be issued by first interrupting configuration and

reprogramming I/O pins using the ACTIVE_DISENGAGE and CONFIG_IO instructions.

The CONFIG_IO instruction allows I/O buffers to be configured using the JTAG port

and when issued after the ACTIVE_DISENGAGE instruction interrupts configuration.

This instruction allows you to perform board-level testing prior to configuring the

Cyclone III device family or waiting for a configuration device to complete

configuration. Prior to issuing the CONFIG_IO instruction, you must issue the

ACTIVE_DISENGAGE

instruction. This is because in Cyclone III device family, the

CONFIG_IO

instruction does not hold nSTATUS low until reconfiguration, so you must

disengage the active configuration mode controller when active configuration is

interrupted. The ACTIVE_DISENGAGE instruction places the active configuration mode

controllers in an idle state prior to JTAG programming. Additionally, the

ACTIVE_ENGAGE

instruction allows you to re-engage a disengaged active configuration

mode controller.

1 You must follow a specific flow when executing the CONFIG_IO, ACTIVE_DISENGAGE,

and ACTIVE_ENGAGE JTAG instructions in Cyclone III device family. For more

information about the instruction flow, refer to “JTAG Instructions” on page 9–60.

The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on

Cyclone III device family do not affect JTAG boundary-scan or programming

operations. Toggling these pins does not affect JTAG operations (other than the usual

boundary-scan operation).

When designing a board for JTAG configuration, consider the dedicated configuration

pins. Table 9–16 lists how these pins must be connected during JTAG configuration.

Table 9–16. Dedicated Configuration Pin Connections During JTAG Configuration

Signal

Description

nCE

On all Cyclone III device family in the chain, nCE must be driven low by connecting it to ground, pulling it

low using a resistor or driving it by some control circuitry. For devices that are also in multi-device AS, AP,

PS, or FPP configuration chains, the nCE pins must be connected to GND during JTAG configuration or

JTAG configured in the same order as the configuration chain.

nCEO

On all Cyclone III device family in the chain, nCEO is left floating or connected to the nCE of the next

device.

MSEL[3..0]

These pins must not be left floating. These pins support whichever non-JTAG configuration that is used in

production. If you only use JTAG configuration, tie these pins to GND.

nCONFIG

Driven high by connecting to the VCCIO supply of the bank in which the pin resides and pulling up using a

resistor or driven high by some control circuitry.

nSTATUS

Pull to the VCCIO supply of the bank in which the pin resides using a 10-k resistor. When configuring

multiple devices in the same JTAG chain, each nSTATUS pin must be pulled up to the VCCIO individually.

CONF_DONE

Pull to the VCCIO supply of the bank in which the pin resides using a 10-k resistor. When configuring

multiple devices in the same JTAG chain, each CONF_DONE pin must be pulled up to the VCCIO supply of

the bank in which the pin resides individually. CONF_DONE going high at the end of JTAG configuration

indicates successful configuration.

DCLK

Must not be left floating. Drive low or high, whichever is more convenient on your board.

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