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AD5303/AD5313/AD5323

Rev. B | Page 22 of 28

OPTO-ISOLATED INTERFACE FOR PROCESS

CONTROL APPLICATIONS

The AD5303/AD5313/AD5323 has a versatile 3-wire serial

interface making it ideal for generating accurate voltages in

process control and industrial applications. Due to noise, safety

requirements, or distance, it may be necessary to isolate the

AD5303/AD5313/AD5323 from the controller. This can easily

be achieved by using opto-isolators, which provides isolation

in excess of 3 kV. The serial loading structure of the AD5303/

AD5313/AD5323 makes it ideally suited for use in opto-isolated

applications. Figure 42 shows an opto-isolated interface to the

AD5303/AD5313/AD5323 where DIN, SCLK, and SYNC are

driven from opto-couplers. The power supply to the part also

needs to be isolated. This is done by using a transformer. On the

DAC side of the transformer, a 5 V regulator provides the 5 V

supply required for the AD5303/AD5313/AD5323.

SCLK

DIN

AD5303/AD5313/

AD5323

SYNC

REGULATOR

POWER

VDD

10µF

0.1µF

VOUTA

VOUTB

VREFB

VREFA

VDD

10kΩ

DIN

SYNC

SCLK

VDD

GND BUF A BUF B

Figure 42. AD5303/AD5313/AD5323 in an Opto-Isolated Interface

DECODING MULTIPLE AD5303/AD5313/AD5323s

The SYNC pin on the AD5303/AD5313/AD5323 can be used

in applications to decode a number of DACs. In this application,

all the DACs in the system receive the same serial clock and

serial data, but only the SYNC to one of the devices is active at

any one time, allowing access to two channels in this 8-channel

system. The 74HC139 is used as a 2-to-4 line decoder to address

any of the DACs in the system. To prevent timing errors from

occurring, the enable input should be brought to its inactive

state while the coded address inputs are changing state.

Figure 43 shows a diagram of a typical setup for decoding

multiple AD5303/AD5313/AD5323 devices in a system.

SCLK

DIN

SCLK

AD5303/

AD5313/

AD5323

SYNC

74HC139

ENABLE

CODED

ADDRESS

DGND

1Y0

1Y1

1Y2

1Y3

VCC

VDD

DIN

SCLK

AD5303/

AD5313/

AD5323

SYNC

DIN

SCLK

AD5303/

AD5313/

AD5323

SYNC

DIN

SCLK

AD5303/

AD5313/

AD5323

SYNC

Figure 43. Decoding Multiple AD5303/AD5313/AD5323 Devices in a System

AD5303/AD5313/AD5323 AS A DIGITALLY

PROGRAMMABLE WINDOW DETECTOR

A digitally programmable upper/lower limit detector using

the two DACs in the AD5303/AD5313/AD5323 is shown in

Figure 44. The upper and lower limits for the test are loaded

to DAC A and DAC B, which, in turn, set the limits on the

CMP04. If the signal at the VIN input is not within the pro-

grammed window, an LED indicates the fail condition.

1/2

CMP04

FAIL

PASS

1/6 74HC05

VREF

SCLK

DIN

VOUTA

VDD

AD5303/AD5313/

AD5323

VREFA

GND

0.1µF

10µF

1kΩ

VIN

PASS/FAIL

DIN

SCLK

SYNC

VREFB

VOUTB

Figure 44. Window Detector Using AD5303/AD5313/AD5323

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