AD5303 datasheet(23/28 Pages) AD

23 / 28 page

AD5303/AD5313/AD5323

Rev. B | Page 23 of 28

COARSE AND FINE ADJUSTMENT USING THE

AD5303/AD5313/AD5323

The DACs in the AD5303/AD5313/AD5323 can be paired

together to form a coarse and fine adjustment function, as

shown in Figure 45. DAC A provides the coarse adjustment

while DAC B provides the fine adjustment. Varying the ratio

of R1 and R2 changes the relative effect of the coarse and fine

adjustments. With the resistor values and external reference

shown, the output amplifier has unity gain for the DAC A

output, so the output range is 0 V to 2.5 V − 1 LSB. For

DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B

a range equal to 19 mV.

The circuit is shown with a 2.5 V reference, but reference

voltages up to VDD may be used. The op amps indicated allow

a rail-to-rail output swing.

GND

AD5303/AD5313/

AD5323

EXT 2.5V

REF

VOUT

VOUTB

VREFA

1µF

GND

VIN

0.1µF

10µF

VDD

VDD = 5V

+5V

AD820/

OP295

VOUTA

VREFB

51.2kΩ

390Ω

VOUT

900Ω

51.2kΩ

AD780/REF192

WITH VDD = 5V

Figure 45. Coarse and Fine Adjustment

DAISY-CHAIN MODE

This mode is used for updating serially connected or standalone

devices on the rising edge of SYNC. For systems that contain

several DACs, or where the user wishes to read back the DAC

contents for diagnostic purposes, the SDO pin may be used to

daisy-chain several devices together and provide serial readback.

By connecting the daisy-chain enable (DCEN) pin high, the

daisy-chain mode is enabled. It is tied low in standalone mode.

In daisy-chain mode, the internal gating on SCLK is disabled.

The SCLK is continuously applied to the input shift register

when SYNC is low. If more than 16 clock pulses are applied,

the data ripples out of the shift register and appears on the SDO

line. This data is clocked out after the falling edge of SCLK and

is valid on the subsequent rising and falling edges. By connect-

ing this line to the DIN input on the next DAC in the chain, a

multiDAC interface is constructed. Sixteen clock pulses are

required for each DAC in the system. Therefore, the total

number of clock cycles must equal 16N, where N is the total

number of devices in the chain. When the serial transfer to all

devices is complete, SYNC should be taken high. This prevents

any further data from being clocked into the input shift register.

A continuous SCLK source may be used if it can be arranged

that SYNC is held low for the correct number of clock cycles.

Alternatively, a burst clock containing the exact number of

clock cycles may be used and SYNC may be taken high some

time later.

When the transfer to all input registers is complete, a common

LDAC signal updates all DAC registers and all analog outputs

are updated simultaneously.

68HC111

MISO

MOSI

SCK

PC7

PC6

DIN

SCLK

AD5303/

AD5313/

AD53231

(DAC 1)

SYNC

LDAC

SDO

SCLK

AD5303/

AD5313/

AD53231

(DAC 2)

SYNC

LDAC

SDO

DIN

SCLK

AD5303/

AD5313/

AD53231

(DAC N)

SYNC

LDAC

SDO

DIN

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 46. Daisy-Chain Mode

AD5303 Datasheet(PDF) 23 Page - Analog Devices

AD5303 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL