ADUM5401 datasheet(21/28 Pages) AD

21 / 28 page

Data Sheet

ADuM5401/ADuM5402/ADuM5403/ADuM5404

Rev. C | Page 21 of 28

APPLICATIONS INFORMATION

The dc-to-dc converter section of the ADuM5401/ADuM5402/

ADuM5403/ADuM5404 works on principles that are common to

most switching power supplies. It has a secondary side controller

architecture with isolated pulse-width modulation (PWM)

feedback. VDD1 power is supplied to an oscillating circuit that

switches current into a chip scale air core transformer. Power

transferred to the secondary side is rectified and regulated to

either 3.3 V or 5 V. The secondary (VISO) side controller regulates

the output by creating a PWM control signal that is sent to the

primary (VDD1) side by a dedicated iCoupler data channel. The

PWM modulates the oscillator circuit to control the power being

sent to the secondary side. Feedback allows for significantly higher

power and efficiency.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 implement

undervoltage lockout (UVLO) with hysteresis on the VDD1 power

input. This feature ensures that the converter does not enter

oscillation due to noisy input power or slow power-on ramp rates.

PCB LAYOUT

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 digital

isolators with 0.5 W isoPower integrated dc-to-dc converter

require no external interface circuitry for the logic interfaces.

Power supply bypassing is required at the input and output

supply pins (see Figure 25). Note that low ESR bypass capacitors

are required between Pin 1 and Pin 2 and between Pin 15 and

Pin 16, as close to the chip pads as possible.

The power supply section of the ADuM5401/ADuM5402/

ADuM5403/ADuM5404 uses a 180 MHz oscillator frequency

to pass power efficiently through its chip scale transformers. In

addition, the normal operation of the data section of the iCoupler

introduces switching transients on the power supply pins. Bypass

capacitors are required for several operating frequencies. Noise

suppression requires a low inductance, high frequency capacitor;

ripple suppression and proper regulation require a large value

capacitor. These are most conveniently connected between Pin 1

and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VISO.

To suppress noise and reduce ripple, a parallel combination of

at least two capacitors is required. The recommended capacitor

values are 0.1 μF and 10 μF for VDD1 and VISO. The smaller

capacitor must have a low ESR; for example, use of a ceramic

capacitor is advised.

The total lead length between the ends of the low ESR capacitor

and the input power supply pin must not exceed 2 mm. Installing

the bypass capacitor with traces more than 2 mm in length may

result in data corruption. Consider bypassing between Pin 1 and

Pin 8 and between Pin 9 and Pin 16 unless both common ground

pins are connected together close to the package.

VDD1

GND1

VIA/VOA

VIB/VOB

VISO

GNDISO

VOA/VIA

VOB/VIB

VIC/VOC

VOC/VIC

VOD

RCOUT

VID

VSEL

GND1

BYPASS < 2mm

GNDISO

Figure 25. Recommended PCB Layout

In applications involving high common-mode transients, ensure

that board coupling across the isolation barrier is minimized.

Furthermore, design the board layout such that any coupling that

does occur affects all pins equally on a given component side.

Failure to ensure this can cause voltage differentials between

pins exceeding the absolute maximum ratings for the device

as specified in Table 19, thereby leading to latch-up and/or

permanent damage.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are power

devices that dissipate approximately 1 W of power when fully

loaded and running at maximum speed. Because it is not possible

to apply a heat sink to an isolation device, the devices primarily

depend on heat dissipation into the PCB through the GND

pins. If the devices are used at high ambient temperatures, provide

a thermal path from the GND pins to the PCB ground plane.

The board layout in Figure 25 shows enlarged pads for Pin 8 and

Pin 9. Large diameter vias should be implemented from the pad to

the ground, and power planes should be used to reduce inductance.

Multiple vias should be implemented from the pad to the ground

plane to significantly reduce the temperature inside the chip.

The dimensions of the expanded pads are at the discretion of

the designer and depend on the available board space.

THERMAL ANALYSIS

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 parts

consist of four internal die attached to a split lead frame with two

die attach paddles. For the purposes of thermal analysis, the die

is treated as a thermal unit, with the highest junction temperature

reflected in the θJA from Table 14. The value of θJA is based on

measurements taken with the parts mounted on a JEDEC standard,

4-layer board with fine width traces and still air. Under normal

operating conditions, the ADuM5401/ADuM5402/ADuM5403/

ADuM5404 devices operate at full load across the full temperature

range without derating the output current. However, following the

recommendations in the PCB Layout section decreases thermal

resistance to the PCB, allowing increased thermal margins in

high ambient temperatures.

ADUM5401 Datasheet(PDF) 21 Page - Analog Devices

ADUM5401 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL