LM5109ASD datasheet(3/16 Pages) TI

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LM5109A

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SNVS412A – APRIL 2006 – REVISED MARCH 2013

PIN DESCRIPTIONS (continued)

Pin #

NAME

DESCRIPTION

APPLICATION INFORMATION

SOIC

WSON(1)

Connect the positive terminal of the bootstrap capacitor to HB and

High side gate driver positive

the negative terminal of the bootstrap capacitor to HS. The bootstrap

supply rail

capacitor should be placed as close to IC as possible.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2)

VDD to VSS

–0.3V to 18V

HB to HS

−0.3V to 18V

LI or HI to VSS

−0.3V to VDD + 0.3V

LO to VSS

−0.3V to VDD + 0.3V

HO to VSS

VHS − 0.3V to VHB + 0.3V

HS to VSS

(3)

−5V to 90V

HB to VSS

108V

Junction Temperature

–40°C to 150°C

Storage Temperature Range

−55°C to 150°C

ESD Rating HBM(4)

1.5 kV

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test

conditions, see the Electrical Characteristics .

(2)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3)

In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally

not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated

voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15V. For example, if

VDD = 10V, the negative transients at HS must not exceed –5V.

(4)

The human body model is a 100 pF capacitor discharged through a 1.5k

Ω resistor into each pin.

Recommended Operating Conditions

VDD

8V to 14V

HS(1)

−1V to 90V

VHS + 8V to VHS + 14V

HS Slew Rate

< 50 V/ns

Junction Temperature

−40°C to 125°C

(1)

In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally

not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated

voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15V. For example, if

VDD = 10V, the negative transients at HS must not exceed –5V.

Electrical Characteristics

Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction

temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO

(1).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supply Currents

IDD

VDD quiescent current

LI = HI = 0V

0.3

0.6

IDDO

VDD operating current

f = 500 kHz

1.8

2.9

IHB

Total HB quiescent current

LI = HI = 0V

0.06

0.2

IHBO

Total HB operating current

f = 500 kHz

1.4

2.8

(1)

Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through

correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

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