LM2665 datasheet(2/16 Pages) TI

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LM2665

SNVS009F – NOVEMBER 1999 – REVISED MAY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2)

V+ to GND Voltage:

5.8V

OUT to GND Voltage:

11.6V

OUT to V+ Voltage:

5.8V

(GND

− 0.3V) to (V+ + 0.3V)

V+ and OUT Continuous Output Current

50 mA

Output Short-Circuit Duration to GND(3)

1 sec.

Continuous Power

600 mW

Dissipation (TA = 25°C)

(4)

TJMax

(4)

150°C

θJA

(4)

210°C/W

Operating Junction Temperature Range

−40° to 85°C

Storage Temperature Range

−65°C to +150°C

Lead Temp. (Soldering, 10 seconds)

300°C

ESD Rating

2kV

(1)

Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when

operating the device beyond its rated operating conditions.

(2)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3)

OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and should be

avoided. Also, for temperatures above 85°C, OUT must not be shorted to GND or V+, or device may be damaged.

(4)

The maximum allowable power dissipation is calculated by using PDMax = (TJMax − TA)/θJA, where TJMax is the maximum junction

temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance of the specified package.

Electrical Characteristics

Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: V+ = 5V, C1 = C2 = 3.3 μF.

(1)

Symbol

Parameter

Condition

Min

Typ

Max

Units

(2)

(3)

(2)

V+

Supply Voltage

2.5

5.5

Supply Current

No Load

650

1250

µA

ISD

Shutdown Supply Current

µA

VSD

Shutdown Pin Input Voltage

Shutdown Mode

2.0

(4)

Normal Operation

0.8

(5)

Output Current

RSW

Sum of the Rds(on)of the four internal

IL = 40 mA

3.5

MOSFET switches

ROUT

Output Resistance(6)

IL = 40 mA

fOSC

Oscillator Frequency

(7)80

160

kHz

fSW

Switching Frequency

(7)

kHz

PEFF

Power Efficiency

RL (1.0k) between GND and OUT

IL = 40 mA to GND

(1)

In the test circuit, capacitors C1 and C2 are 3.3 µF, 0.3Ω maximum ESR capacitors. Capacitors with higher ESR will increase output

resistance, reduce output voltage and efficiency.

(2)

Min. and Max. limits are guaranteed by design, test, or statistical analysis.

(3)

Typical numbers are not guaranteed but represent the most likely norm.

(4)

The minimum input high for the shutdown pin equals 40% of V+.

(5)

The maximum input low of the shutdown pin equals 20% of V+.

(6)

Specified output resistance includes internal switch resistance and capacitor ESR. See the details in the application information for

positive voltage doubler.

(7)

The output switches operate at one half of the oscillator frequency, fOSC = 2fSW.

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