dt

+

15 mA

C

gd

TPS2320

TPS2321

SLVS276F – MARCH 2000 – REVISED JULY 2013

www.ti.com

Table 3. Some Available N-Channel MOSFETs (continued)

CURRENT RANGE

PART NUMBER

DESCRIPTION

MANUFACTURER

(A)

IRF7401

International Rectifier

MMSF5N02HDR2

ON Semiconductor

2 to 5

IRF7313

International Rectifier

SI4410

Vishay Dale

IRLR3103

International Rectifier

5 to 10

IRLR2703

International Rectifier

TIMER

For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. A capacitor

should be connected between TIMER and ground. The presence of an overcurrent condition on either channel of

the TPS2320/TPS2321 causes a 50-

μA current source to begin charging this capacitor. If the over-current

condition persists until the capacitor has been charged to approximately 0.5 V, the TPS2320/TPS2321 latches off

the offending channels and pulls the FAULT pin low. The timer capacitor can be made as large as desired to

provide additional time delay before registering a fault condition. PWRGDx will not correctly report power

conditions when the device is disabled. The time delay is approximately:

OUTPUT-VOLTAGE SLEW-RATE CONTROL

When enabled, the TPS2320/TPS2321 controllers supply the gates of each external MOSFET transistor with a

current of approximately 15

μA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain

(1)

If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external

MOSFET and ground.

VREG CAPACITOR

The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-µF or

0.22-µF ceramic capacitor is recommended.

GATE-DRIVE CIRCUITRY

The TPS2320/TPS2321 includes four separate features associated with each gate-drive terminal:

•

A charging current of approximately 15

μA is applied to enable the external MOSFET transistor. This current

is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1

or DISCH2) of 9 V–12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFET

source terminals to ensure proper operation of this circuitry.

•

A discharge current of approximately 75

μA is applied to disable the external MOSFET transistor. Once the

transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO

discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while

ensuring that the gates of the external MOSFET transistors remain at a low voltage.

•

During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOS

transistors. These transistors continue to operate even if IN1 and IN2 are both at 0 V. This circuitry also helps

hold the external MOSFET transistors off when power is suddenly applied to the system.

•

During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent condition

will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from

the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO

driver is enabled instead. If one channel experiences an overcurrent condition and the other does not, then

only the channel that is conducting excessive current will be turned off rapidly. The other channel will continue

to operate normally.

16

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