TSB41AB1 datasheet(4/70 Pages) TI

4 / 70 page

TSB41AB1

IEEE 1394a2000 ONEPORT CABLE

TRANSCEIVER/ARBITER

SLLS423I − JUNE 2000 − REVISED MARCH 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

description (continued)

required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is

in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it

to normal operation.

When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a

low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the

TSB41AB1 disables its internal clock generators and also disables various voltage and current reference

circuits depending on the state of the port (some reference circuitry must remain active in order to detect new

cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the

ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt

enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a

port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify

the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected

on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes

active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high

when the TSB41AB1 is in the low-power mode.

The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the

C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when

the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is

inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet

addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output

when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON

output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON

to be active.

PHP package terminal diagram

14 15

AGND

AVDD

AGND

TPBIAS

TPA+

TPA−

TPB+

TPB−

AGND

AVDD

SYSCLK

CTL0

CTL1

17 18 19 20

47 46 45 44 43

40 39 38

21 22 23 24

PHP PACKAGE

(TOP VIEW)

TSB41AB1

NOTE A: For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor.

TSB41AB1 Datasheet(PDF) 4 Page - Texas Instruments

TSB41AB1 Datasheet(HTML) 4 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL