ADF4153 datasheet(4/24 Pages) AD

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ADF4153

Data Sheet

Rev. F | Page 4 of 24

SPECIFICATIONS

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;

dBm referred to 50 Ω.

Table 1.

Parameter

B Version1

Y Version2

Unit

Test Conditions/Comments

RF CHARACTERISTICS (3 V)

See Figure 12 for input circuit

RF Input Frequency (RFIN)

0.5/4.0

GHz min/max

B Version: −8 dBm minimum/0 dBm maximum

0.5/4.0

GHz min/max

Y Version: −6.5 dBm minimum/0 dBm maximum

For lower frequencies, ensure slew rate (SR) > 400 V/µs

1.0/4.0

GHz min/max

−10 dBm/0 dBm minimum/maximum

REFERENCE CHARACTERISTICS

See Figure 11 for input circuit

REFIN Input Frequency

10/250

MHz min/max

For f < 10 MHz, use a dc-coupled, CMOS-compatible

square wave; slew rate > 25 V/µs

REFIN Input Sensitivity

0.7/AVDD

V p-p min/max

Biased at AVDD/23

REFIN Input Capacitance

pF max

REFIN Input Current

±100

µA max

PHASE DETECTOR

Phase Detector Frequency4

MHz max

CHARGE PUMP

ICP Sink/Source

Programmable; see Table 9

High Value

mA typ

With RSET = 5.1 kΩ

Low Value

312.5

µA typ

Absolute Accuracy

2.5

% typ

With RSET = 5.1 kΩ

RSET Range

1.5/10

kΩ min/max

ICP Three-State Leakage Current

4.5

nA typ

Sink and source current

Matching

% typ

0.5 V < VCP < VP – 0.5

ICP vs. VCP

% typ

0.5 V < VCP < VP – 0.5

ICP vs. Temperature

% typ

VCP = VP/2

LOGIC INPUTS

VINH, Input High Voltage

1.4

V min

VINL, Input Low Voltage

0.6

V max

IINH/IINL, Input Current

±1

µA max

CIN, Input Capacitance

pF max

LOGIC OUTPUTS

VOH, Output High Voltage

1.4

V min

Open-drain 1 kΩ pull-up to 1.8 V

VOL, Output Low Voltage

0.4

V max

IOL = 500 µA

POWER SUPPLIES

AVDD

2.7/3.3

V min/V max

DVDD, SDVDD

AVDD

AVDD/5.5

V min/V max

IDD

mA max

20 mA typical

Low Power Sleep Mode

µA typ

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