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AD1836AASZ Datasheet(PDF) 6 Page - Analog Devices |
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AD1836AASZ Datasheet(HTML) 6 Page - Analog Devices |
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6 / 24 page  AD1836A Data Sheet Rev. A | Page 6 of 24 Table 7. Timing Specifications Parameter Comments Min Max Unit MASTER CLOCK AND RESET tMH MCLK High 512 × fS Mode 18 ns tML MCLK Low 512 × fS Mode 18 ns tMCLK MCLK Period 512 × fS Mode 36 ns fMCLK MCLK Frequency 512 × fS Mode 27 MHz tPDR PD/RST Low 5 ns tPDRR PD/RST Recovery Reset to Active Output 4500 tMCLK SPI PORT tCHH CCLK High 10 ns tCHL CCLK Low 10 ns tCDS CDATA Setup To CCLK Rising 5 ns tCDH CDATA Hold From CCLK Rising 5 ns tCLS CLATCH Setup To CCLK Rising 5 ns tCLH CLATCH Hold From CCLK Falling 5 ns tCODE COUT Enable From CCLK Falling 10 ns tCOD COUT Delay From CCLK Falling 10 ns tCOH COUT Hold From CCLK Falling 0 ns tCOTS COUT Three-State From CCLK Falling 10 ns DAC SERIAL PORT (Normal Modes) tDBH DBCLK High 15 ns tDBL DBCLK Low 15 ns fDB DBCLK Frequency 64 × fS ns tDLS DLRCLK Setup To DBCLK Rising 0 ns tDLH DLRCLK Hold From DBCLK Rising 10 ns tDDS DSDATA Setup To DBCLK Rising 0 ns tDDH DSDATA Hold From DBCLK Rising 20 ns DAC SERIAL PORT (Packed 128 Mode, Packed 256 Mode) tDBH DBCLK High 15 ns tDBL DBCLK Low 15 ns fDB DBCLK Frequency 256 × fS ns tDLS DLRCLK Setup To DBCLK Rising 0 ns tDLH DLRCLK Hold From DBCLK Rising 10 ns tDDS DSDATA Setup To DBCLK Rising 0 ns tDDH DSDATA Hold From DBCLK Rising 20 ns ADC SERIAL PORT (Normal Modes) tABD ABCLK Delay From MCLK Transition, 256 × fS Mode From MCLK Rising, 512 × fS Mode 15 ns tALS LRCLK Skew From ABCLK Falling –2 +2 ns tABDD ASDATA Delay From ABCLK Falling 5 ns ADC SERIAL PORT (Packed 128 Mode, Packed 256 Mode) tABD ABCLK Delay From MCLK Transition, 256 × fS Mode From MCLK Rising, 512 × fS Mode 15 ns tALS LRCLK Skew From ABCLK Falling –2 +2 ns tABDD ASDATA Delay From ABCLK Falling 5 ns ADC SERIAL PORT (TDM Packed AUX) tABD ABCLK Delay From MCLK Transition, 256 × fS Mode From MCLK Rising, 512 × fS Mode 15 ns tALS LRCLK Skew From ABCLK Falling –2 +2 ns tABDD ASDATA Delay From ABCLK Falling 5 ns tDDS DSDATA1 Hold To ABCLK Rising 0 ns tDDH DSDATA1 Hold From ABCLK Rising 7 ns AUXILIARY INTERFACE tAXDS AAUXDATA Setup To AUXBCLK Rising 7 ns tAXDH AAUXDATA Hold From AUXBCLK Rising 10 ns tDXDD DAUXDATA Delay From AUXBCLK Falling 25 ns |
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