AD1836A

Data Sheet

Rev. A | Page 16 of 24

FSTDM

ADC L0

ADC L1

AUX_ADC L0 AUX_ADC L1

ADC R0

INTERNAL

ADC R1

AUX_ADC R0 AUX_ADC R1

DAC L0

DAC L1

DAC L2

AUX_DAC L0

DAC R0

DAC R1

DAC R2

AUX_DAC R0

MSB TDM

1ST

CH

LEFT

RIGHT

––MSB LEFT

BCLK

TDM

ASDATA1

TDM (OUT)

ASDATA1

DSDATA1

DSDATA1

AUX

(FROM AUX ADC NO. 1)

AUX

(FROM AUX ADC NO. 1)

AAUXDATA1 (IN)

(FROM AUX ADC NO. 1)

AAUXDATA2 (IN)

(FROM AUX ADC NO. 2)

DAUXDATA (OUT)

(TO AUX DAC)

NOTE

AUX BCLK FREQUENCY IS 64

× FRAME RATE; TDM BCLK FREQUENCY IS 256 × FRAME RATE.

FSTDM FOLLOWS AUX LRCLK BY 3 1/2 ± 1/2 TDM BCLK IN BOTH MASTER AND SLAVE MODES.

MSB TDM

8TH

CH

32

32

1ST

CH

MSB TDM

8TH

CH

TDM (IN)

INTERNAL

INTERNAL

INTERNAL

MSB TDM

INTERNAL

INTERNAL

INTERNAL

INTERNAL

INTERNAL

INTERNAL

––MSB LEFT

––MSB LEFT

––MSB RIGHT

––MSB RIGHT

––MSB RIGHT

Figure 9. AUX Mode Timing (Note that the Clocks Are Not to Scale)