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AD5161

Data Sheet

Rev. B | Page 16 of 20

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

A-to-B. Unlike the polarity of VDD to GND, which must be

positive, voltage across A-B, W-A, and W-B can be at either

polarity.

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper-to-B starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across terminal AB divided by the 256 positions

of the potentiometer divider. The general equation defining the

output voltage at VW with respect to ground for any valid input

voltage applied to terminals A and B is

256

)

(

−

(3)

For a more accurate calculation, which includes the effect of

wiper resistance, VW, can be found as

256

)

(

256

)

(

)

(

(4)

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly on

the ratio of the internal resistors RWA and RWB and not the

absolute values. Therefore, the temperature drift reduces to

15 ppm/°C.

PIN SELECTABLE DIGITAL INTERFACE

The AD5161 provides the flexibility of a selectable interface.

When the digital interface select (DIS) pin is tied low, the SPI

mode is engaged. When the DIS pin is tied high, the I2C mode

is engaged.

SPI Compatible 3-Wire Serial Bus (DIS = 0)

The AD5161 contains a 3-wire SPI compatible digital interface

(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB

first. The format of the word is shown in Table 6.

The positive-edge sensitive CLK input requires clean transitions

to avoid clocking incorrect data into the serial input register.

Standard logic families work well. If mechanical switches are

used for product evaluation, they should be debounced by a

flip-flop or other suitable means. When CS is low, the clock

loads data into the serial register on each positive clock edge

(see Figure 37).

The data setup and data hold times in the specification table

determine the valid timing requirements. The AD5161 uses an

8-bit serial input data register word that is transferred to the

internal RDAC register when the CS line returns to logic high.

Extra MSB bits are ignored.

Daisy-Chain Operation

The serial data output (SDO) pin contains an open-drain

N-channel FET. This output requires a pull-up resistor in order

to transfer data to the next package’s SDI pin. This allows for

daisy-chaining several RDACs from a single processor serial

data line. The pull-up resistor termination voltage can be larger

than the VDD supply voltage. It is recommended to increase the

clock period when using a pull-up resistor to the SDI pin of the

following device because capacitive loading at the daisy-chain

node SDO-SDI between devices may induce time delay to

subsequent devices. Users should be aware of this potential

problem to achieve data transfer successfully (see Figure 43). If

two AD5161s are daisy-chained, a total of at least 16 bits of data

is required. The first eight bits, complying with the format

shown in Table 6, go to U2 and the second eight bits with the

same format go to U1. CS should be kept low until all 16 bits are

clocked into their respective serial registers. After this, CS is

pulled high to complete the operation and load the RDAC latch.

If the data word during the CS low period is greater than 16

bits, any additional MSBs will be discarded.

AD5161

µC

SDI

CLK

SDO

CLK

SDI

SDO

MOSI

VDD

2.2k

Ω

Figure 43. Daisy-Chain Configuration

I2C Compatible 2-Wire Serial Bus (DIS = 1)

The AD5161 can also be controlled via an I2C compatible serial

bus with DIS tied high. The RDACs are connected to this bus as

slave devices.

The first byte of the AD5161 is a slave address byte (see Table 7

and Table 8). It has a 7-bit slave address and a R/W bit. The six

MSBs of the slave address are 010110, and the following bit is

determined by the state of the AD0 pin of the device. AD0

allows the user to place up to two of the I2C compatible devices

on one bus.

The 2-wire I2C serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 40). The

following byte is the slave address byte, which consists of

the 7-bit slave address followed by an R/W bit (this bit

determines whether data will be read from or written to

the slave device).

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