APW7290 datasheet(12/18 Pages) ANPEC

12 / 18 page

Rev. A.2 - Jun., 2013

www.anpec.com.tw

APW7290

Application Information (Cont.)

Thermal Consideration

In most applications, the APW7290 does not dissipate

much heat due to its high efficiency. But, in applications

where the APW7290 is running at high ambient tempera-

ture with low supply voltage and high duty cycles, the heat

dissipated may exceed the maximum junction tempera-

ture of the part. If the junction temperature reaches ap-

proximately 150°C, both power switches will be turned

off and the SW node will become high impedance.

To avoid the APW7290 from exceeding the maximum junc-

tion temperature, the user will need to do some thermal

analysis. The goal of the thermal analysis is to deter-

mine whether the power dissipated exceeds the maxi-

mum junction temperature of the part. The power dissi-

pated by the part is approximated:

D ≅ IOUT

2 x (R

P-FET x D+RN-FET x (1-D))

The temperature rise is given by:

R = (PD)(θJA)

Where P

D is the power dissipated by the regulator, D is

duty cycle of main switch

D = V

OUT/VIN

The

JA is the thermal resistance from the junction of the

die to the ambient temperature. The junction temperature,

J, is given by:

J = TA + TR

Where T

A is the ambient temperature.

Output Capacitor Selection (Cont.)

LIM

PEAK

OUT

P-FET

∆I

The maximum power dissipation on the device can be

shown as follow figure:

Layout Consideration

For all switching power supplies, the layout is an impor-

tant step in the design; especially at high peak currents

and switching frequencies. If the layout is not carefully

done, the regulator might show noise problems and duty

cycle jitter.

1. The input capacitor should be placed close to the VIN

and GND. Connecting the capacitor and VIN/GND with

short and wide trace without any via holes for good

input voltage filtering. The distance between VIN/GND

to capacitor less than 2mm respectively is

recommended.

2. To minimize copper trace connections that can inject

noise into the system, the inductor should be placed

as close as possible to the SW pin to minimize the

noise coupling into other circuits.

3. The output capacitor should be place closed to con-

verter VOUT and GND.

4. Since the feedback pin and network is a high imped-

ance circuit the feedback network should be routed

away from the inductor. The feedback pin and feed-

back network should be shielded with a ground plane

or trace to minimize noise coupling into this circuit.

5. A star ground connection or ground plane minimizes

ground shifts and noise is recommended.

Junction Temperature(

oC)

-50

-25

100

125

150

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

APW7290 Datasheet(PDF) 12 Page - Anpec Electronics Coropration

APW7290 Datasheet(HTML) 12 Page - Anpec Electronics Coropration

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL