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TPS53513 Datasheet(PDF) 21 Page - Texas Instruments

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Part # TPS53513
Description  1.5 to 18 V Input, 8-A Single Synchronous Step-Down SWIFT Converter
PDF  33 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS53513 Datasheet(HTML) 21 Page - Texas Instruments

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(
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-
´
=
+
=
+
´
´ ´
´
´
IND(ripple)
IN
OUT
OUT
TRIP
TRIP
OCP
SW
IN
DS(on)
DS(on)L
I
V
V
V
V
V
1
I
2
2 L f
V
8 R
8 R
=
´
TRIP
TRIP
TRIP
V
R
I
TPS53513
www.ti.com
SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013
Power-Good
The TPS53513 has power-good output that indicates high when switcher output is within the target. The power-
good function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of
the target value, internal comparators detect the power-good state and the power-good signal becomes high
after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal
becomes low after a 2-
μs internal delay. The power-good output is an open-drain output and must be pulled-up
externally.
Current Sense and Overcurrent Protection
The TPS53513 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent trip level. In order to provide good accuracy and a cost-effective solution, the TPS53513 supports
temperature compensated MOSFET RDS(on) sensing. Connect the TRIP pin to GND through the trip-voltage
setting resistor, RTRIP. The TRIP terminal sources ITRIP current, which is 10 μA typically at room temperature, and
the trip level is set to the OCL trip voltage VTRIP as shown in Equation 5.
where
•
VTRIP is in mV
•
RTRIP is in kΩ
•
ITRIP is in µA
(5)
The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly
connected to the drain terminal of the low-side MOSFET. ITRIP has a 3000-ppm/°C temperature slope to
compensate the temperature dependency of RDS(on). The GND pin acts as the positive current-sensing node.
Connect the GND pin to the proper current sensing device, (for example, the source terminal of the low-side
MOSFET.)
Because the comparison occurs during the OFF state, VTRIP sets the valley level of the inductor current. Thus,
the load current at the overcurrent threshold, IOCP, is calculated as shown in Equation 6.
where
•
RDS(on)L is the on-resistance of the low-side MOSFET
•
RTRIP is in kΩ
(6)
Equation 6 calculates the typical DC OCP level (typical low-side on-resistance [RDS(on)] of 5.9 mΩ should be
used); in order to design for worst case minimum OCP, maximum low-side on-resistance value of 8 m
Ω should
be used.
During an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the
output voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold
and shuts down.
For the TPS53513, the overcurrent protection maximum is recommended up to 12 A only.
Overvoltage and Undervoltage Protection
The TPS53513 monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage. When the
feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an
internal UVP delay counter begins counting. After 1 ms, the TPS53513 latches OFF both high-side and low-side
MOSFETs drivers. The UVP function enables after soft-start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching
a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again for a minimum on-time. The TPS53513 operates in this cycle until the output voltage is
pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is
latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by re-toggling EN pin.
Copyright © 2013, Texas Instruments Incorporated
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