8905

3-PHASE BRUSHLESS DC

MOTOR CONTROLLER/DRIVER

Adaptive Commutation Delay. The

adaptive commutation delay circuit uses the

back-EMF zero-crossing indicator signal

(FCOM) to determine an optimal commutation

time for efficient synchronous operation. This

circuit commutates the outputs, delayed from the

last zero crossing, using two external timing

between crossings.

Dwg. WP-016-2

FCOM

t FCOM

tCD1

VCWD

V

CD1

VCD2

t CD2

where

2.5 V reference while FCOM is high. When

discharged at approximately twice the charging

except on the opposite phase of FCOM . Thus

the commutations occur approximately halfway

between zero crossings. The actual delay is

slightly less than halfway to compensate for

electrical delays in the motor, which improves

efficiency.

Because the commutation-delay capacitors

are adaptive in nature, the absolute value and

tolerance is not critical. In choosing these

capacitors, the voltage excursion should be 1.5 V to 2.5 V at rated speed.

Solving for C in the equation I = Cdv/dt, where dv = 2.5 V, I = 22

µA, and

Use of a capacitor slightly greater than this value will ensure that the commuta-

tion delay capacitors never charge to the high rail.

Blanking and Watchdog Timing Functions. The blanking and watchdog

where

t

and

The CWD capacitor begins charging at each commutation, initiating the

BLANK signal. BLANK is an internal signal that inhibits the back-EMF

comparators during the commutation transients, preventing errors due to

inductive recovery and voltage settling transients.

Dwg. WP-022

BLANK

CWD

V

V

TL

20/RPM

#motor poles

WATCHDOG-TRIGGERED COMMUTATION

V

TL

Dwg. WP-021

BLANK

CWD

V

NORMAL COMMUTATION