8905

3-PHASE BRUSHLESS DC

MOTOR CONTROLLER/DRIVER

acquire and minimizes settling. The Current Control Block Diagram illustrates

the YANK signal and its effects.

Braking. A dynamic braking feature of the A8905CLB shorts the three

motor windings to ground. This is accomplished by turning the three source

drivers OFF and the three sink drivers ON. Activation of the brake can be

implemented through the BRAKE input or through the D2 bit in the serial port.

function to remain active after power failure. Power-down braking with delay can

be implemented by using an external RC and other components to control the

brake terminal, as shown. Brake delay can be set using the equation below to

ensure that voice-coil head retract occurs before the spindle motor brake is

activated. Once the brake is activated, due to the inherent capacitive input, the

three sink drivers will remain active until the device is reset.

BRAKE

FAULT

VBRK

V

– V

FAULT

D

BRAKE

ACTIVATED

Dwg. OP-004

R

B

CB

t

BRK

Centertap. The A8905CLB internally

simulates the centertap voltage of the motor.

To obtain reliable start-up performance from

motor to motor, the motor centertap should be

connected to this terminal.

Serial Port. The serial port functions to

write various operational and diagnostic modes

to the A8905CLB. The serial port DATA IN is

enabled/disabled by the CHIP SELECT

terminal. When CHIP SELECT is high the

serial port is disabled and the chip is not

affected by changes in data at the DATA IN or

CLOCK terminals.

To write data to the serial port, the

CLOCK terminal should be low prior to the

CHIP SELECT terminal going low. Once

CHIP SELECT goes low, information on the

DATA IN terminal is read into the shift register

on the positive-going transition of the CLOCK.

There are 24 bits in the serial input port.

Data written into the serial port is latched

and becomes active upon the low-to-high

transition of the CHIP SELECT terminal at the

end of the write cycle. D0 will be the last bit

written to the serial port.

Reset. The RESET terminal (when pulled

low) clears all serial port bits, including the D0

latch, which puts the A8905CLB in the sleep

mode.

Dwg. EP-036-1

INDEX

CHIP SELECT

+5 V

VRET

C

WD

C D2

CD1

RESET

CLOCK

DATA IN

V

BB

C

ST

RES

C

CF2

R F1

CF1

BYPASS

0.22

µF

BYPASS

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

DD

V

BB

V

FLL

MUX

COMMUTATION

DELAY

BOOST

CHARGE

PUMP

OSC (REF)

DATA OUT

FAULT

RB

CB

TYPICAL

APPLICATION