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TS30011/12/13

Version 1.6

Specifications subject to change

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Copyright © 2012, Triune Systems, LLC

Switching output, VSW

This is the switching node of the regulator. It should be connected directly to the 4.7uH inductor with a wide, short trace and to

one end of the Bootstrap capacitor. It is switching between VCC and PGND at the switching frequency.

Ground, GND

This ground is used for the majority of the device including the analog reference, control loop, and other circuits.

Power Ground, PGND

This is a separate ground connection used for the low side synchronous switch to isolate switching noise from the rest of the

device. (Figure 23)

Enable, high-voltage, EN

This is the input terminal to activate the regulator. The input threshold is TTL/CMOS compatible. It also has an internal pull-

up to ensure a stable state if the pin is disconnected.

Power Good Output, PG

This is an open drain, active low output. The switched mode output voltage is monitored and the PG line will remain low until

threshold, an internal delay timer is activated and the PG line is de-asserted to high once this delay timer expires. In the event

and the delay timer times out. See Figure 2 for the circuit schematic for the PG signal.

INTERNAL PROTECTION DETAILS

Internal Current Limit

The current through the high side FET is sensed on a cycle by cycle basis and if current limit is reached, it will abbreviate the

cycle. In addition, the device senses the FB pin to identify hard short conditions and will direct the VSW output to skip 4 cycles

if current limit occurs when FB is low. This allows current built up in the inductor during the minimum on time to decay

sufficiently. Current limit is always active when the regulator is enabled. Soft start ensures current limit does not prevent

regulator startup.

Under extended over current conditions (such as a short), the device will automatically disable. Once the over current

condition is removed, the device returns to normal operation automatically. (Alternately the factory can configure the device’s

NVM to shutdown the regulator if an extended over current event is detected and require a toggle of the Enable pin to return

the device to normal operation.)

Thermal Shutdown

If the temperature of the die exceeds 170°C (typical), the VSW outputs will tri-state to protect the device from damage. The PG

and all other protection circuitry will stay active to inform the system of the failure mode. Once the device cools to 160°C

(typical), the device will start up again, following the normal soft start sequence. If the device reaches 170°C, the

shutdown/restart sequence will repeat.

Reference Soft Start

The reference in this device is ramped at a rate of 4ms to prevent the output from overshoot during startup. This ramp restarts

whenever there is a rising edge sensed on the Enable pin. This occurs in both the fixed and adjustable versions. During the soft

start ramp, current limit is still active, and will still protect the device in case of a short on the output.

Output Overvoltage

If the output of the regulator exceeds 103% of the regulation voltage, the VSW outputs will tri-state to protect the device from

damage. This check occurs at the start of each switching cycle. If it occurs during the middle of a cycle, the switching for that

cycle will complete, and the VSW outputs will tri-state at the beginning of the next cycle.

VCC Under-Voltage Lockout

The device is held in the off state until VCC reaches 4.5V (typical). There is a 500mV hysteresis on this input, which requires the

input to fall below 4.0V (typical) before the device will disable.