 2004 Microchip Technology Inc.

DS21908A-page 5

MCP6S91/2/3

DIGITAL CHARACTERISTICS

Parameters

Sym

Min

Typ

Max

Units

Conditions

SPI Inputs (CS, SI, SCK)

Logic Threshold, Low

0

—

V

Input Leakage Current

-1.0

—

+1.0

µA

Logic Threshold, High

V

Amplifier Output Leakage Current

—

-1.0

—

1.0

µA

In Shutdown mode

SPI Output (SO, for MCP6S93)

Logic Threshold, Low

V

Logic Threshold, High

—

SPI Timing

Pin Capacitance

—

10

—

pF

All digital I/O pins

Input Rise/Fall Times (CS, SI, SCK)

——

2

µs

(Note 1)

Output Rise/Fall Times (SO)

—5

—

ns

MCP6S93

CS High Time

40

—

—

ns

SCK Edge to CS Fall Setup Time

10

—

—

ns

SCK edge when CS is high

CS Fall to First SCK Edge Setup Time

40

—

—

ns

SCK Frequency

——

10

MHz

SCK High Time

40

—

—

ns

SCK Low Time

40

—

—

ns

SCK Last Edge to CS Rise Setup Time

30

—

—

ns

CS Rise to SCK Edge Setup Time

100

—

—

ns

SCK edge when CS is high

SI Setup Time

40

—

—

ns

SI Hold Time

10

—

—

ns

SCK to SO Valid Propagation Delay

—

—

80

ns

MCP6S93

CS Rise to SO Forced to Zero

—

—

80

ns

MCP6S93

Channel and Gain Select Timing

Channel Select Time

—

1.5

—

µs

CHx = 0.6V, CHy = 0.3V, G = 1,

CHx to CHy select,

Gain Select Time

—

1

—

µs

CHx = CHy = 0.3V,

G = 5 to G = 1 select,

Shutdown Mode Timing

Out of Shutdown mode (CS goes high)

to Amplifier Output Turn-on Time

—3.5

10

µs

Into Shutdown mode (CS goes high) to

Amplifier Output High-Z Turn-off Time

—1.5

—

µs

Note

1:

Not tested in production. Set by design and characterization.

2:

When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of