PIC16 datasheet(237/418 Pages) MICROCHIP

237 / 418 page

 2011-2013 Microchip Technology Inc.

DS40001609C-page 237

PIC16(L)F1508/9

22.0 ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

system.

Full-Duplex

mode

useful

for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

The EUSART module includes the following capabilities:

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in synchronous

modes

• Sleep operation

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 22-1 and Figure 22-2.

The EUSART transmit output (TX_out) is available to

the TX/CK pin and internally to the following peripherals:

• Configurable Logic Cell (CLC)

FIGURE 22-1:

EUSART TRANSMIT BLOCK DIAGRAM

TXREG register

Pin Buffer

and Control

TXIF

TRMT

TX9D

Data bus

TXIE

Interrupt

TX/CK

TX_out

TX9

TXEN

Transmit Shift Register (TSR)

(8)

MSb

LSB

÷ n

Multiplier

SYNC

BRGH

BRG16

x16

x64

+ 1

SPBRGH SPBRGL

Baud Rate Generator

FOSC

BRG16

Rev. 10-000113A

8/1/2013

PIC16 Datasheet(PDF) 237 Page - Microchip Technology

PIC16 Datasheet(HTML) 237 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL