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ISP1507B Datasheet(PDF) 21 Page - NXP Semiconductors |
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ISP1507B Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 81 page ![]() ISP1507A_ISP1507B_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 May 2008 21 of 81 NXP Semiconductors ISP1507A; ISP1507B ULPI HS USB OTG transceiver If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1507 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 6. The recommended power-up sequence for the link is as follows: 1. The link waits for 1 ms, ignoring all the ULPI pin status. 2. The link may start to detect DIR status level. If DIR is detected as LOW for three clock cycles, the link may send a RESET command. The ULPI interface is ready for use. |
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