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MP6920 Datasheet(PDF) 6 Page - Monolithic Power Systems

Part # MP6920
Description  Fast Turn-Off Intelligent Rectifier
PDF  9 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP6920 Datasheet(HTML) 6 Page - Monolithic Power Systems

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MP6920- FAST TURN-OFF INTELLIGENT RECTIFIER
MP6920 Rev. 1.01
www.MonolithicPower.com
6
9/19/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
OPERATION
The MP6920 supports operation in discontinuous
conduction mode (DCM) and Quasi-Resonant
Flyback converters. The internal control circuitry
of the MP6920 controls the integrated MOSFET
gate in forward mode and will turn the gate off
when the MOSFET current is fairly low.
Blanking
The control circuitry contains a blanking function.
When it pulls the integrated MOSFET on/off, it
makes sure that the on/off state at least lasts for
some time. The turn-on blanking time is 1.6µs,
which determines the minimum on-time. During
the turn-on blanking period, the turn-off threshold
is not totally blanked, but changes to +50mV
(instead of -30mV). This ensures that the part
can always turn off even during the turn-on
blanking period (albeit slower).
Under-Voltage Lockout
When VDD is below the under-voltage lockout
(UVLO) threshold, the part enters sleep mode
and the integrated MOSFET will not turn on.
Basic Operation
The basic operations of flyback converter with
the MP6920 are:
Turn-On Phase
When the switch current flows through the
body diode of the integrated MOSFET, it
generates a negative VDS (VD-VSS) across it
(<-500mV); the VDS is much lower than the
turn-on threshold of the control circuitry (-
70mV), which then turns on the integrated
MOSFET after a 200ns turn-on delay
(defined in Figure 2).
Conducting Phase
When the integrated MOSFET turns on, VDS
(-ISD x RDS(ON)) rises according to the switch
current (ISD) drop: As soon as VDS rises
above the turn-on threshold (-70mV), the
control circuitry stops pulling up the internal
gate driver and the driver voltage of the
integrated MOSFET drops, which makes the
MOSFET ON-resistance RDS(ON) larger. By
doing that, VDS (-ISD x RDS(ON)) stabilizes to
around -70mV even when the switch current
ISD is fairly small. This function can avoid
triggering the turn-off threshold (-30mV) of
the internal driver until the current through
the integrated MOSFET has dropped to near
zero.
Figure 3 shows the MP6920 operating in
heavy-load condition. Due to the high current,
the internal driver voltage initially saturates;
after VDS goes to above -70mV, driver
voltage decreases to adjust the VDS to
around -70mV.
Figure 4 shows the MP6920 operating at
light-load condition. Due to the low current,
the driver voltage never saturates but begins
to decrease as soon as the integrated
MOSFET turns on and adjusts the VDS.
Turn-Off Phase
When VDS rises to trigger the turn-off
threshold (-30mV), the driver voltage of the
switch goes zero after a 20ns turn-off delay
(shown in Figure 2) by the control circuitry.
Similar to turn-on phase, a 200ns blanking
time after the switch turns off avoid
erroneous trigging.
Light-Load Latch-Off Function
The gate driver of integrated MOSFET in the
MP6920 is latched to save the driver loss at light-
load condition to improve light-load efficiency.
The light-load-enter pulse width (tLL) is internally
fixed at 2.2μs. During each switching cycle, if the
integrated MOSFET conducting period remains
below 2.2µs, the MP6920 falls into light-load
mode and latches off the integrated MOSFET
after a 120µs delay (light-load-enter delay, tLL-Delay)
After entering light-load mode, the MP6920
monitors the integrated MOSFET’s body diode
conducting period by sensing VDS—when VDS
exceeds -250mV (VLL-DS), the MP6920 treats the
integrated MOSFET as a body diode until the
conducting period finishes. If the MOSFET’s
body diode conducting period is longer than
2.4µs (tLL+tLL-H), the light-load mode finishes and
the integrated MOSFET of MP6920 is unlatched
to restart the internal synchronous rectification
(see Figure 6 for details).



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