MP28258 – 3A, 4.2V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)

MP28258 Rev 1.14

www.MonolithicPower.com

14

9/25/2012

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start up performance. In case one wants to use

larger Cdc for a better FB noise immunity,

combined with reduced R1 and R2 to limit the

Cdc in a reasonable value without affecting the

system start up. Be noted that even when the

Cdc is applied, the load and line regulation are

still Vramp related.

Figure12—Simplified Circuit of Ceramic

Capacitor with DC blocking capacitor

Input Capacitor

The input current to the step-down converter is

discontinuous and therefore requires a capacitor

to supply the AC current to the step-down

converter while maintaining the DC input voltage.

Ceramic capacitors are recommended for best

performance and should be placed as close to

X7R ceramic dielectrics are recommended

because they are fairly stable with temperature

fluctuations.

The capacitors must also have a ripple current

rating greater than the maximum input ripple

current of the converter. The input ripple current

can be estimated as follows:

OUT

OUT

CIN

OUT

IN

IN

VV

II

(1

)

VV

=×

× −

(16)

where:

OUT

CIN

I

I

2

=

(17)

For simplification, choose the input capacitor with

an RMS current rating greater than half of the

maximum load current.

The input capacitance value determines the input

voltage ripple of the converter. If there is an input

voltage ripple requirement in the system, choose

the input capacitor that meets the specification.

The input voltage ripple can be estimated as

follows::

OUT

OUT

OUT

IN

SW

IN

IN

IN

IV

V

V(1

)

FC

V

V

Δ=

×

× −

×

(18)

OUT

IN

SW

IN

I

1

V

4F

C

Δ= ×

×

(19)

Output Capacitor

The output capacitor is required to maintain the

DC output voltage. Ceramic or POSCAP

capacitors are recommended. The output voltage

ripple can be estimated as:

OUT

OUT

OUT

ESR

SW

IN

SW

OUT

VV

1

V(1

) (R

)

FL

V

8 F

C

Δ=

× −

×

+

××

×

(20)

In the case of ceramic capacitors, the impedance

at the switching frequency is dominated by the

capacitance. The output voltage ripple is mainly

caused by the capacitance. For simplification, the

output voltage ripple can be estimated as:

OUT

OUT

OUT

2

SW

OUT

IN

VV

V(1

)

8F

L C

V

Δ=

× −

×× ×

(21)

The output voltage ripple caused by ESR is very

small. Therefore, an external ramp is needed to

stabilize the system. The external ramp can be

generated through resistor R4 and capacitor C4

following equation 5, 8 and 9.

In the case of POSCAP capacitors, the ESR

dominates the impedance at the switching

frequency. The ramp voltage generated from the

ESR is high enough to stabilize the system.

Therefore, an external ramp is not needed. A

minimum ESR value around 12mΩ is required to

ensure stable operation of the converter. For

simplification,

the

output

ripple

can

be

approximated as:

OUT

OUT

OUT

ESR

SW

IN

VV

V(1

) R

FL

V

Δ=

× −

×

×

(22)

Maximum output capacitor limitation should be

also considered in design application. MP28258

has an around 1ms soft-start time period. If the

output capacitor value is too high, the output

voltage can’t reach the design value during the