Data Sheet

AD7739

Rev. A | Page 19 of 32

CHANNEL CONVERSION TIME REGISTERS

8 Bits, Read/Write Registers, Address 0x30 to

Address 0x37, Default Value 0x91

The conversion time registers enable or disable chopping and

configure the digital filter for a particular channel (see Table 25

and Table 26). This register value affects the conversion time,

frequency response, and noise performance of the ADC.

MODE REGISTER

8 Bits, Read/Write Register, Address 0x38 to

Address 0x3F, Default Value 0x00

The mode register configures the part and determines its operating

mode (see Table 27, Table 28, and Table 29). Writing to the

mode register clears the ADC status register, sets the RDY pin

to a logic high level, exits all current operations, and starts the

mode specified by the mode bits.

The AD7739 contains only one mode register. The two LSBs of

the address are used for writing to the mode register to specify

the channel selected for the operation determined by the MD2

to MD0 bits. Only the address 0x38 must be used for reading

from the mode register.

Table 25. Channel Conversion Time Registers Bits

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

Chop

FW (7-bit filter word)

Default

1

0x11

Table 26. Channel Conversion Time Registers Bit Descriptions

Bit

Mnemonic

Description

7

Chop

Chopping enable bit. Set to 1 to apply chopping mode for a particular channel.

6 to 0

FW

Chop = 1, single conversion or continuous conversion with one channel enabled.

Conversion Time (µs) = (FW × 128 + 262)/MCLK Frequency (MHz), the FW range is 2 to 127.

Chop = 1, continuous conversion with two or more channels enabled.

Conversion Time (µs) = (FW × 128 + 263)/MCLK Frequency (MHz), the FW range is 2 to 127.

Chop = 0, single conversion or continuous conversion with one channel enabled.

Conversion Time (µs) = (FW × 64 + 213)/MCLK Frequency (MHz), the FW range is 3 to 127.

Chop = 0, continuous conversion with two or more channels enabled.

Conversion Time (µs) = (FW × 64 + 214)/MCLK Frequency (MHz), the FW range is 3 to 127.

Table 27. Mode Register Bits

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

MD2

MD1

MD0

CLKDIS

Dump

Cont RD

24/16 BIT

Clamp

Default

0

0

0

0

0

0

0

0

Table 28. Mode Register Bit Descriptions

Bit

Mnemonic

Description

7 to 5

MD2 to MD0

Mode bits. These three bits determine the AD7739 operation mode. Writing a new value to the mode bits exit

the part from the mode in which it has been operating and place it in the newly requested mode immediately.

The function of the mode bits follows.

MD2

MD1

MD0

Mode

Address Used for Mode Register Write

Specifies

0

0

0

Idle

0

0

1

Continuous conversion

First channel to start converting

0

1

0

Single conversion

Channel to convert

0

1

1

Power-down (standby)

1

0

0

ADC zero-scale self-calibration

Conversion time for calibration

1

0

1

ADC full-scale self-calibration (for 2.5 V)

Conversion time for calibration

1

1

0

Channel zero-scale system calibration

Channel to calibrate

1

1

1

Channel full-scale system calibration

Channel to calibrate