A3P030 datasheet(207/220 Pages) MICROSEMI

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Revision 13

5-1

5 – Datasheet Information

List of Changes

The following table lists critical changes that were made in each version of the ProASIC3 datasheet.

Revision

Changes

Page

Revision 13

(January 2013)

The "ProASIC3 Ordering Information" section has been updated to mention "Y" as

"Blank" mentioning "Device Does Not Include License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43104).

1-III

Added a note to Table 2-2 • Recommended Operating Conditions 1,2 (SAR 43644):

The programming temperature range supported is Tambient = 0°C to 85°C.

2-2

The note in Table 2-115 • ProASIC3 CCC/PLL Specification referring the reader to

SmartGen was revised to refer instead to the online help associated with the core

(SAR 42569).

2-89

Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip

(SoC) throughout the document (SAR 40284).

Live at Power-Up (LAPU) has been replaced with ’Instant On’.

Revision 12

(September 2012)

The "Security" section was modified to clarify that Microsemi does not support

read-back of programmed data.

1-1

Added a Note stating "VMV pins must be connected to the corresponding VCCI pins.

See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information.

" to

Table 2-1 • Absolute Maximum Ratings and Table 2-2 • Recommended Operating

Conditions 1,2 (SAR 38321).

2-1

2-2

Table 2-35 • Duration of Short Circuit Event Before Failure was revised to change

the maximum temperature from 110°C to 100°C, with an example of six months

instead of three months (SAR 37933).

2-30

In Table 2-93 • Minimum and Maximum DC Input and Output Levels, VIL and VIH

were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR

28549).

2-67

Figure 2-36 • FIFO Read and Figure 2-37 • FIFO Write are new (SAR 28371).

2-98

The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"

section in the "Pin Descriptions" chapter: "Within the package, the VMV plane is

decoupled from the simultaneous switching noise originating from the output buffer

VCCI domain" and replaced with “Within the package, the VMV plane biases the

input stage of the I/Os in the I/O banks” (SAR 38321). The datasheet mentions that

"VMV pins must be connected to the corresponding VCCI pins" for an ESD

enhancement.

3-1

A3P030 Datasheet(PDF) 207 Page - Microsemi Corporation

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