A3P030 datasheet(208/220 Pages) MICROSEMI

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5-2

Revision 13

Revision 11

(March 2012)

Note indicating that A3P015 is not recommended for new designs has been added.

The "Devices Not Recommended For New Designs" section is new (SAR 36760).

I to IV

The following sentence was removed from the "Advanced Architecture" section: "In

addition, extensive on-chip programming circuitry allows for rapid, single-voltage

(3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface" (SAR

34687).

1-3

The reference to guidelines for global spines and VersaTile rows, given in the

"Global Clock Contribution—PCLOCK" section, was corrected to the "Spine

Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric

User's Guide (SAR 34734).

2-12

Figure 2-3 • Input Buffer Timing Model and Delays (example) has been modified for

the DIN waveform; the Rise and Fall time label has been changed to tDIN (35430).

2-15

The AC Loading figures in the "Single-Ended I/O Characteristics" section were

updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O

Software Settings" section (SAR 34883).

2-31

Added values for minimum pulse width and removed the FRMAX row from

Table 2-107 through Table 2-114 in the "Global Tree Timing Characteristics" section.

Use the software to determine the FRMAX for the device you are using (SARs

37279, 29269).

2-84

Revision 10

(September 2011)

The "In-System Programming (ISP) and Security" section and "Security" section

were revised to clarify that although no existing security measures can give an

absolute guarantee, Microsemi FPGAs implement the best security available in the

industry (SAR 32865).

I, 1-1

The value of 34 I/Os for the QN48 package in A3P030 was added to the "I/Os Per

Package 1" section (SAR 33907).

The Y security option and Licensed DPA Logo were added to the "ProASIC3

Ordering Information" section. The trademarked Licensed DPA Logo identifies that a

product is covered by a DPA counter-measures license from Cryptography

Research (SAR 32151).

III

The "Specifying I/O States During Programming" section is new (SAR 21281).

1-7

In Table 2-2 • Recommended Operating Conditions 1,2, VPUMP programming

voltage in programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45" (SAR

30666). It was corrected in v2.0 of this datasheet in April 2007 but inadvertently

changed back to “3.0 to 3.6 V” in v1.4 in August 2009. The following changes were

made to Table 2-2 • Recommended Operating Conditions 1,2:

VCCPLL analog power supply (PLL) was changed from "1.4 to 1.6" to "1.425 to

1.575" (SAR 33850).

For VCCI and VMV, values for 3.3 V DC and 3.3 V DC Wide Range were corrected.

The correct value for 3.3 V DC is "3.0 to 3.6 V" and the correct value for 3.3 V Wide

Range is "2.7 to 3.6" (SAR 33848).

2-2

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings was

update to restore values to the correct columns. Previously the Slew Rate column

was missing and data were aligned incorrectly (SAR 34034).

2-23

The notes regarding drive strength in the "Summary of I/O Timing Characteristics –

Default I/O Software Settings" section and "3.3 V LVCMOS Wide Range" section

tables were revised for clarification. They now state that the minimum drive strength

for the default software configuration when run in wide range is ±100 µA. The drive

strength displayed in software is supported in normal range only. For a detailed I/V

curve, refer to the IBIS models (SAR 25700).

2-21, 2-38

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