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AM28F020 Datasheet(PDF) 15 Page - Advanced Micro Devices |
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AM28F020 Datasheet(HTML) 15 Page - Advanced Micro Devices |
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15 / 35 page ![]() Am28F020 15 the Erase-verify command (section D). Addresses are latched on the falling edge of the WE# pulse. Another software timing routine (6 µs duration) must be executed to allow for generation of internal voltages for margin checking and read operation (section E). During Erase-verification (section F) each address that returns FFh data is successfully erased. Each address of the array is sequentially verified in this manner by re- peating sections D thru F until the entire array is veri- fied or an address fails to verify. Should an address location fail to verify to FFh data, erase the device again. Repeat sections A thru F. Resume verification (section D) with the failed address. Each data change sequence allows the device to use up to 1,000 erase pulses to completely erase. Typically 100 erase pulses are required. Note: All address locations must be programmed to 00h prior to erase. This equalizes the charge on all memory cells and ensures reliable erasure. FLASHRITE PROGRAMMING SEQUENCE Program Setup The device is programmed byte by byte. Bytes may be programmed sequentially or at random. Program Setup is the first of a two-cycle program command. It stages the device for byte programming. The Program Setup operation is performed by writing 40h to the command register. Program Only after the program Setup operation is completed will the next WE# pulse initiate the active programming operation. The appropriate address and data for pro- gramming must be available on the second WE# pulse. Addresses and data are internally latched on the falling and rising edge of the WE# pulse respectively. The ris- ing edge of WE# also begins the programming opera- tion. You must write the Program-verify command to terminate the programming operation. This two step sequence of the Setup and Program commands helps to ensure that memory contents are not accidentally written. Also, programming can only occur when high voltage is applied to the VPP pin and all control pins are in their proper state. In absence of this high voltage, memory contents cannot be programmed. Refer to AC Characteristics and Waveforms for specific timing parameters. Program Verify Command Following each programming operation, the byte just programmed must be verified. Write C0h into the command register in order to initiate the Program-verify operation. The rising edge of this WE pulse terminates the programming operation. The Program-verify operation stages the device for verifica- tion of the last byte programmed. Addresses were pre- viously latched. No new information is required. Margin Verify During the Program-verify operation, the device applies an internally generated margin voltage to the ad- dressed byte. A normal microprocessor read cycle out- puts the data. A successful comparison between the programmed byte and the true data indicates that the byte was successfully programmed. The original pro- grammed data should be stored for comparison. Pro- gramming then proceeds to the next desired byte location. Should the byte fail to verify, reprogram (refer to Program Setup/Program). Figure 3 and Table 5 indi- cate how instructions are combined with the bus oper- ations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for spe- cific timing parameters. Flashrite Programming Algorithm The device Flashrite Programming algorithm employs an interactive closed loop flow to program data byte by byte. Bytes may be programmed sequentially or at ran- dom. The Flashrite Programming algorithm uses 10 µs programming pulses. Each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed. The program al- gorithm allows for up to 25 programming operations per byte per reprogramming cycle. Most bytes verify after the first or second pulse. The entire sequence of pro- gramming and byte verification is performed with high voltage applied to the VPP pin. Figure 3 and Table 5 il- lustrate the programming algorithm. |
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