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AD8842 Datasheet(PDF) 2 Page - Analog Devices |
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AD8842 Datasheet(HTML) 2 Page - Analog Devices |
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2 / 13 page  AD8842–SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H Resolution N 8 Bits Integral Nonlinearity Error INL ±0.2 ±1 LSB Differential Nonlinearity DNL All Devices Monotonic ±0.4 ±1 LSB Full-Scale Gain Error GFSE 2 LSB Output Offset VBZE PR = 0, Sets D = 80H 525 mV Output Offset Drift TCVBZ PR = 0, Sets D = 80H 5 µV/°C VOLTAGE INPUTS—Applies to All Inputs VINx Input Voltage Range 1 IVR ±3 ±4V Input Resistance RIN 12 19 k Ω Input Capacitance CIN 9pF DAC OUTPUTS—Applies to All Outputs VOUTx Voltage Range 1 OVR RL = 10 kΩ± 3 ±4V Output Current IOUT ∆V OUT < 1.5 LSB ±3mA Capacitive Load CL No Oscillation 500 pF DYNAMIC PERFORMANCE—Applies to All DACs Full Power Gain Bandwidth 1 GBW VINx = ± 3 VP, RL = 2 kΩ, CL = 10 pF 10 50 kHz Slew Rate Measured 10% to 90% Positive SR+ ∆V OUTx = +5.5 V 0.5 1.0 V/ µs Negative SR– ∆V OUTx = –5.5 V 1.0 1.8 V/ µs Total Harmonic Distortion THD VINx = 4 V p-p, D = FFH, f = 1 kHz, 0.01 % fLPF = 80 kHz, RL = 1 kΩ Spot Noise Voltage eN f = 1kHz, VIN = 0 V 78 nV/ √Hz Output Settling Time tS ±1 LSB Error Band, D = 00 H to FFH 2.9 µs D = FFH to 00H 5.4 µs Channel-to-Channel Crosstalk CT Measured Between Adjacent Channels, f = 100 kHz 72 dB Digital Feedthrough Q VINx = 0 V, D = 0 to 25510 5 nV-s POWER SUPPLIES Positive Supply Current IDD PR = 0 V 10 14 mA Negative Supply Current ISS PR = 0 V 9 13 mA Power Dissipation 2 PDISS 95 135 mW Power Supply Rejection PSRR PR = 0 V, ∆V DD = ± 5% 0.0001 0.01 %/% Power Supply Range PSR VDD, |VSS| 4.75 5.00 5.25 V DIGITAL INPUTS Logic High VIH 2.4 V Logic Low VIL 0.8 V Input Current IL ±10 µA Input Capacitance CIL 7pF Input Coding Offset Binary DIGITAL OUTPUT Logic High V OH I OH = –0.4 mA 3.5 V Logic Low V OL I OL = 1.6 mA 0.4 V TIMING SPECIFICATIONS 1 Input Clock Pulse Width tCH, tCL 60 ns Data Setup Time tDS 40 ns Data Hold Time tDH 20 ns CLK to SDO Propagation Delay tPD 80 ns DAC Register Load Pulse Width tLD 70 ns Preset Pulse Width tPR 50 ns Clock Edge to Load Time tCKLD 30 ns Load Edge to Next Clock Edge tLDCK 60 ns NOTES 1Guaranteed by design, not subject to production test. 2Calculated limit = 5 V × (I DD + ISS). Specifications subject to change without notice. REV. –2– (VDD = +5 V, VSS = –5 V, All VINx = +3 V, TA = –40 °C to +85°C, unless otherwise noted.) A |
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