AM53CF94KC datasheet(17/76 Pages) AMD

17 / 76 page

P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

Current Transfer Count Register

(00H, 01H, 0EH) Read Only

Current Transfer Count Register

CTCREG

Address: 00H, 01H, 0EH

Type: Read

CRVL15

CRVL14

CRVL13 CRVL12 CRVL11 CRVL10

CRVL9

CRVL8

xxx

xxxxx

76543

210

CRVL7

CRVL6

CRVL5

CRVL4

CRVL3

CRVL2

CRVL1

CRVL0

xxx

xxxxx

CRVL23

CRVL22

CRVL21

CRVL20 CRVL19 CRVL18

CRVL17

CRVL16

xxx

xxxxx

17348B-16

CTCREG – Bits 23:0 – CRVL 23:0 – Current

Value 23:0

This is a three-byte register which decrements to keep

track of the number of bytes transferred during a DMA

transfer. Reading these registers returns the current

value of the counter. The counter will decrement by one

for every byte and by two for every word transferred. The

transaction is complete when the count reaches zero,

and bit 4 of the Status Register (04H) is set. Should the

sequence terminate early, the sum of the values in the

Current FIFO (07H) and the Current Transfer Count

The least significant byte is located at address 00H, the

middle byte is located at address 01H, and the most sig-

nificant byte is located at address 0EH. Register 0EH

extends the total width of the register from 16 to 24

bits, and is only enabled when the Enable Features

bit (bit 6) of Control Register Two is set to a value

of ‘1’.

These registers are automatically loaded with the val-

ues in the Start Transfer Count Register every time a

DMA command is issued. However, following a chip or

power on reset, up until the time register 0EH is loaded,

the Am53CF94/96’s part-unique ID can be obtained by

reading register 0EH.

In the Target mode, this counter is decremented by the

active edge of

DACK during the Data-In phase and by

REQC during the Data-Out phase.

In the Initiator mode, the counter is decremented by the

active edge of

DACK during the Synchronous Data-In

phase or by

ACKC during the Asynchronous Data-In

phase and by

DACK during the Data-Out phase.

Start Transfer Count Register

(00H, 01H, 0EH) Write Only

Start Transfer Count Register

STCREG

Address: 00H–01H

Type: Write

STVL15

STVL14

STVL13

STVL12

STVL11

STVL10

STVL9

STVL8

xxxxx

xxx

765

43210

STVL7

STVL6

STVL5

STVL4

STVL3

STVL2

STVL1

STVL0

xxx

xxxxx

STVL23

STVL22

STVL21

STVL20 STVL19

STVL18

STVL17 STVL16

xxx

xxxxx

17348B-17

STCREG – Bits 15:0 – STVL 15:0 – Start Value 15:0

This is a three-byte register which contains the number

of bytes to be transferred during a DMA operation. The

value in the Start Transfer Count Register must be pro-

grammed prior to command execution.

The least significant byte is located at address 00H, the

middle byte is located at address 01H, and the most sig-

nificant byte is located at address 0EH. Register 0EH

extends the total width of the register from 16 to 24 bits,

and is only enabled when the Enable Features bit (bit 6)

of Control Register Two is set to a value of ‘1’. This sets

the maximum transfer count to 16.78 MBytes. When a

value of ‘0’ is written to these registers, the transfer

count will be set to the maximum. A DMA NOP com-

mand must be issued before the transfer counter values

can be written to 00H, 01H, and 0EH.

These registers retain their value until overwritten, and

are therefore unaffected by a hardware or software re-

set. This reduces programming redundancy since it is

no longer necessary to reprogram the count for subse-

quent DMA transfers of the same size.

AM53CF94KC Datasheet(PDF) 17 Page - Advanced Micro Devices

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