AM79C960 datasheet(80/127 Pages) AMD

80 / 127 page

P R E L I M I N A R Y

AMD

1-422

Am79C960

Note that bit 13 of TMD1, which was formerly a reserved

bit in the LANCE (Am7990), is assigned a new meaning,

ADD_FCS.

TMD0

Holds LADRF [15:0]. This is combined with HADR [7:0]

in TMD1 to form a 24-bit address of the buffer pointed to

by this descriptor table entry. There are no restrictions

on buffer byte alignment or length.

TMD1

Bit

Name

Description

OWN

This bit indicates that the de-

scriptor entry is owned by the

host

(OWN=0)

the

PCnet-ISA controller (OWN=1).

The host sets the OWN bit after

filling the buffer pointed to by the

descriptor entry. The PCnet-ISA

controller clears the OWN bit af-

ter transmitting the contents of

the buffer. Both the PCnet-ISA

controller and the host must not

alter a descriptor entry after it has

relinquished ownership.

ERR

ERR is the OR of UFLO, LCOL,

LCAR, or RTRY. ERR is written

by the PCnet-ISA controller. This

bit is set in the current descriptor

when the error occurs, and there-

fore may be set in any descriptor

of a chained buffer transmission.

ADD_FCS

ADD_FCS dynamically controls

the generation of FCS on a frame

by frame basis. It is valid only if

the

STP

bit

set.

When

ADD_FCS is set, the state of

DXMTFCS is ignored and trans-

mitter

FCS

generation

activated. When ADD_FCS = 0,

FCS generation is controlled by

DXMTFCS. ADD_FCS is written

by the host, and unchanged by

the PCnet-ISA controller. This

was a reserved bit in the LANCE

(Am7990).

MORE indicates that more than

one re-try was needed to trans-

mit a frame. MORE is written by

the PCnet-ISA controller. This bit

has meaning only if the ENP or

the ERR bit is set.

ONE

ONE indicates that exactly one

re-try was needed to transmit a

frame. ONE flag is not valid when

LCOL is set. ONE is written by

the PCnet-ISA controller. This bit

has meaning only if the ENP or

the ERR bit is set.

DEF

DEFERRED indicates that the

PCnet-ISA controller had to defer

while trying to transmit a frame.

This condition occurs if the chan-

nel is busy when the PCnet-ISA

controller is ready to transmit.

DEF is written by the PCnet-ISA

controller. This bit has meaning

only if the ENP or ERR bits are

set.

STP

START OF PACKET indicates

that this is the first buffer to be

used by the PCnet-ISA controller

for this frame. It is used for data

chaining buffers. The STP bit

must be set in the first buffer of

the frame, or the PCnet-ISA con-

troller will skip over the descriptor

and poll the next descriptor(s)

until the OWN and STP bits are

set.

STP is written by the host and is

not changed by the PCnet-ISA

controller.

ENP

END OF PACKET indicates that

this is the last buffer to be used by

the PCnet-ISA controller for this

frame. It is used for data chaining

buffers. If both STP and ENP are

set, the frame fits into one buffer

and there is no data chaining.

ENP is written by the host and is

not changed by the PCnet-ISA

controller.

7-0

HADR

The HIGH ORDER 8 address

bits of the buffer pointed to by this

descriptor. This field is written by

the host and is not changed by

the PCnet-ISA controller.

TMD2

Bit

Name

Description

15-12 ONES

MUST BE ONES. This field is

written by the host and un-

changed

the

PCnet-ISA

controller.

11-0

BCNT

BUFFER BYTE COUNT is the

length of the buffer pointed to by

this descriptor, expressed as the

two’s com- plement of the length

of the buffer. This is the number

of bytes from this buffer that will

be transmitted by the PCnet-ISA

controller. This field is written by

the host and is not changed by

AM79C960 Datasheet(PDF) 80 Page - Advanced Micro Devices

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