28

AmMCL00XA

PR EL IMIN A R Y

AC CHARACTERISTICS-ALTERNATE CE# CONTROLLED WRITES

Write/Erase/Program Operations

Notes:

1. Rise/fall time

≤10 ns.

2. Maximum specification not needed due to the internal stop timer that will stop any erase or write operation that exceed the

device specification.

3. Card Enable Controlled Programming:

Flash Programming is controlled by the valid combination of the Card Enable (CE1#, CE2#) and Write Enable (WE#) signals.

For systems that use the Card Enable signal(s) to define the write pulse width, all setup, hold, and inactive write enable timing

should be measured relative to the Card Enable signal(s).

4. Under worst case condition of 90

execute the four bus cycle command necessary to program each byte.

Parameter Symbols

Parameter Description

-150

Unit

JEDEC

Standard

tAVAV

tWC

Write Cycle Time

Min

150

ns

tAVEL

tAS

Address Setup Time

Min

10

ns

tELAX

tAH

Address Hold Time

Min

50

ns

tDVEH

tDS

Data Setup Time

Min

50

ns

tEHDX

tDH

Data Hold Time

Min

0

ns

tGLDV

tOEH

Output Enable Hold Time for Embedded Algorithm

Min

10

ns

tGHEL

Read Recovery Time before Write

Min

0

µs

tWLEL

tWS

WE# Setup Time before CE#

Min

0

ns

tEHWH

tWH

WE# Hold Time

Min

0

ns

tELEH

tCP

CE# Pulse Width

Min

50

ns

tEHEL

tCPH

CE# Pulse Width HIGH (Note 3)

Min

20

ns

tEHEH3

Embedded Programming Operation (Notes 3,4)

Typ

9

Max

300

µs

tEHEH4

Embedded Erase Operation for each 64K byte Memory

Sector (Notes 1, 2)

Typ

1.5

Max

15

s

tVCS

VCC Setup Time to Write Enable LOW

Min

50

µs