PALCE20V8 datasheet(16/16 Pages) AMD

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AMD

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PALCE20V8 Family

POWER-UP RESET

The PALCE20V8 has been designed with the capability

to reset during system power-up. Following power-up,

all flip-flops will be reset to LOW. The output state will be

HIGH independent of the logic polarity. This feature pro-

vides extra flexibility to the designer and is especially

valuable in simplifying state machine initialization. A

timing diagram and parameter table are shown below.

Due to the synchronous operation of the power-up reset

and the wide range of ways VCC can rise to its steady

state, two conditions are required to insure a valid

power-up reset. These conditions are:

s The VCC rise must be monotonic.

s Following reset, the clock input must not be driven

from LOW to HIGH until all applicable input and

feedback setup times are met.

Parameter

Symbol

Parameter Description

Min

Max

Unit

tPR

Power-Up Reset Time

1000

Input or Feedback Setup Time

tWL

Clock Width LOW

See Switching

Characteristics

16491D-16

tPR

tWL

4 V

VCC

Power

Registered

Output

Clock

Power-Up Reset Waveforms

PALCE20V8 Datasheet(PDF) 16 Page - Advanced Micro Devices

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