W25Q80BWSVIP datasheet(23/74 Pages) WINBOND

23 / 74 page

W25Q80BW

Publication Release Date: July 30, 2013

- 23 -

Revision J

7.2.8

Read Status Register-1 (05h) and Read Status Register-2 (35h)

The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is

entered by driving /CS

low and shifting the instruction code “05h” for Status Register-1 or “35h” for

Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on

the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in figure 7. The Status

SRP1, QE, LB3-0, CMP and SUS bits (see Status Register section earlier in this datasheet).

The Read Status Register instruction may be used at any time, even while a Program, Erase or Write

Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when

the cycle is complete and if the device can accept another instruction. The Status Register can be read

continuously, as shown in Figure 7. The instruction is completed by driving /CS high.

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (05h or 35h)

High Impedance

Status Register 1 or 2 out

= MSB

Figure 7. Read Status Register Instruction Sequence Diagram

7.2.9

Write Status Register (01h)

The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status

LB1, LB0, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit

locations are read-only and will not be affected by the Write Status Register instruction. LB3-0 are non-

volatile OTP bits, once it is set to 1, it can not be cleared to 0. The Status Register bits are shown in

figure 3a and 3b and described in 8.1.

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have

been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL

must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction

code “01h”, and then writing the status register data byte as illustrated in figure 8.

To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must

have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).

However, SRP1 and LB3, LB2, LB1, LB0 can not be changed from “1” to “0” because of the OTP

protection for these bits. Upon power off, the volatile Status Register bit values will be lost, and the non-

volatile Status Register bit values will be restored when power on again.

W25Q80BWSVIP Datasheet(PDF) 23 Page - Winbond

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