LM2745 datasheet(13/37 Pages) TI

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8 PA

17 PA

Bias Enable

Soft-Start Enable

1.25V

10k

t = 5 ms

VOUT1

VOUT2

1.8V

VSD-IH

1.08V

LM2745, LM2748

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SNOSAL2E – APRIL 2005 – REVISED APRIL 2013

For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the

startup of the master supply and LM2745/8 output voltage was 5 ms, then the desired SD pin slew rate would be

(1.08V/5 ms) = 0.216V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for

RS2 is 1 kΩ. To achieve the desired slew rate, RS1 would then be 274Ω. A timing diagram for this example is

shown in Figure 23.

Figure 23. Delay for Sequencing

SD PIN IMPEDANCE

When connecting a resistor divider to the SD pin of the LM2745/8 some care has to be taken. Once the SD

voltage goes above VSD-IH, a 17 µA pull-up current is activated as shown in Figure 24. This current is used to

create the internal hysteresis (

≊170 mV); however, high external impedances will affect the SD pin logic

thresholds as well. The external impedance used for the sequencing divider network should preferably be a small

fraction of the impedance of the SD pin for good performance (around 1 k

Ω).

Figure 24. SD Pin Logic

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LM2745 Datasheet(PDF) 13 Page - Texas Instruments