PVIN

SW

AGND

FB

PGOOD

EN

SS/TRK

AVIN

COMP

LM20134

L

VCC

PGND

(optional)

SYNC

PVIN

SW

PGND

L

LM20134

LOOP1

LOOP2

LM20134, LM20134Q

www.ti.com

SNVS527G – OCTOBER 2007 – REVISED MARCH 2013

5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or

output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure

feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide

the best output accuracy.

6. Provide adequate device heatsinking. Use as many vias as is possible to connect the DAP to the power

plane heatsink. For best results use a 4x4 via array with a minimum via diameter of 12 mils. See the Thermal

Considerations section to insure enough copper heatsinking area is used to keep the junction temperature

below 125°C.

Figure 36. Schematic of LM20134 Highlighting Layout Sensitive Nodes

Typical Application Circuits

This section provides several application solutions with a bill of materials. All bill of materials reference the below

figure. The compensation for these solutions were optimized to work over a wide range of input and output

outline in the design guide.

Copyright © 2007–2013, Texas Instruments Incorporated

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