REF LEVEL

0.000 dB

0.0 deg

100

1k

START 100.000 Hz

10k

STOP 100 000.000 Hz

/DIV

10.000 dB

45.000 deg

0

GAIN

PHASE

100k

REF LEVEL

0.000 dB

0.0 deg

100

1k

START 50.000 Hz

10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

0

GAIN

PHASE

LM5575

www.ti.com

SNVS471G – JANUARY 2007 – REVISED APRIL 2013

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a

the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable

loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 15kHz was selected. The

frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2

π R4 C5) to

be less than 2kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely,

decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was

selected for 0.01µF and R4 was selected for 49.9k

Ω. These values configure the compensation network zero at

Figure 18. Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

Figure 19. Overall Loop Gain and Phase

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