17

Required timing between Read and Write Commands (tsxx)

There are minimum timing requirements between read and write commands on the serial port.

Figure 19. Timing between two write commands

If the rising edge of the SCLK for the last data bit of the second write command occurs before the 50 microsecond

required delay, then the first write command may not complete correctly.

Figure 20. Timing between write and read commands

If the rising edge of SCLK for the last address bit of the read command occurs before the 50 microsecond required

delay, the write command may not complete correctly.

Figure 21. Timing between read and either write or subsequent read commands

The falling edge of SCLK for the first address bit of either the read or write command must be at least 250 ns after

the last SCLK rising edge of the last data bit of the previous read operation. In addition, during a read operation SCLK

should be delayed after the last address bit to ensure that the ADNS-3090 has time to prepare the requested data.

SCLK

Address

Data

Write Operation

Address

Data

Write Operation

Address

Data

Write Operation

Address

Next Read

Operation

SCLK

Next Read or

Write Operation

Data

Read Operation

Address

Address

SCLK

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PixArt Imaging Inc.

PixArt Imaging Inc.