PIC17C4X datasheet(89/184 Pages) MICROCHIP

89 / 184 page

 2000 Microchip Technology Inc.

DS30605C-page 89

PIC16C63A/65B/73B/74B

13.4

RESETS

13.4.1

POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (parameters D003 and D004, in

the range of 1.5V - 2.1V). To take advantage of the

POR, just tie the MCLR pin directly (or through a resis-

tor) to VDD. This will eliminate external RC components

usually needed to create a POR.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature) must be met to ensure

operation. If these conditions are not met, the device

must be held in RESET until the operating conditions

are met. The device may be held in RESET by keeping

MCLR at Vss.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting.”

13.4.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up from the POR. The PWRT oper-

ates on an internal RC oscillator. The device is kept in

RESET as long as the PWRT is active. The PWRT’s

time delay allows VDD to rise to an acceptable level. A

configuration bit is provided to enable/disable the

PWRT.

The power-up time delay will vary from chip to chip, due

to VDD, temperature and process variation. See DC

parameters for details (TPWRT, parameter #33).

13.4.3

OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer provides a delay of 1024

oscillator cycles (from OSC1 input) after the PWRT

delay, if enabled. This helps to ensure that the crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

13.4.4

BROWN-OUT RESET (BOR)

The configuration bit, BODEN, can enable or disable

the Brown-out Reset circuit. If VDD falls below VBOR

(parameter D005, about 4V) for longer than TBOR

(parameter #35, about 100

µS), the brown-out situation

will reset the device. If VDD falls below VBOR for less

than TBOR, a RESET may not occur.

Once the brown-out occurs, the device will remain in

Brown-out Reset until VDD rises above VBOR. The

Power-up Timer then keeps the device in RESET for

TPWRT (parameter #33, about 72mS). If VDD should fall

below VBOR during TPWRT, the Brown-out Reset pro-

cess will restart when VDD rises above VBOR with the

Power-up Timer Reset. The Power-up Timer is always

enabled when the Brown-out Reset circuit is enabled,

regardless of the state of the PWRT configuration bit.

13.4.5

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows: the

PWRT delay starts (if enabled) when a POR occurs.

Then, OST starts counting 1024 oscillator cycles when

PWRT ends (LP, XT, HS). When the OST ends, the

device comes out of RESET.

If MCLR is kept low long enough, the time-outs will

expire. Bringing MCLR high will begin execution imme-

diately. This is useful for testing purposes or to synchro-

nize more than one PIC16CXX device operating in

parallel.

Table 13-5 shows the RESET conditions for the

STATUS, PCON and PC registers, while Table 13-6

shows the RESET conditions for all the registers.

13.4.6

POWER CONTROL/STATUS

The Brown-out Reset Status bit, BOR, is unknown on a

POR. It must be set by the user and checked on sub-

sequent RESETS to see if bit BOR was cleared, indi-

cating a BOR occurred. The BOR bit is not predictable

if the Brown-out Reset circuitry is disabled.

The Power-on Reset Status bit, POR, is cleared on a

POR and unaffected otherwise. The user must set this

bit following a POR and check it on subsequent

RESETS to see if it has been cleared.

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