TMD37827 datasheet(20/34 Pages) AMSCO

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TMD3782 – 20

Datasheet - Mar. 2013 - V2

The RGBC timing register controls the internal integration time

of the RGBC channel ADCs. Upon power up, the RGBC time

The maximum (or saturation) count value can be calculated

based upon the integration time cycles as follows:

min [CYCLES * 1024, 65535]

Figure TMD3782 – 28:

RGBC Integration Time Register

Wait time is set in 2.38 ms increments unless the WLONG bit is

asserted in which case the wait times are 12× longer. WTIME is

programmed as a 2’s complement number.

Figure TMD3782 – 29:

Wait Time Register

Note:

The wait time register should be configured before AEN and/or PEN is asserted.

Field

Bits

Description (Reset value = 0xFF)

ATIME

7:0

VALUE

CYCLES

TIME

Max Count

0xFF

2.38 ms

1024

0xF6

24 ms

10240

0xD6

100 ms

43008

0xAD

152 ms

65535

0x00

256

609 ms

65535

Field

Bits

Description (Reset value = 0xFF)

WTIME

7:0

WAIT TIME

TIME

(WLONG=0)

TIME

(WLONG=1)

0xFF

2.38 ms

0.03 sec

0xAB

202 ms

2.43 sec

0x00

256

609 ms

7.31 sec

RGBC Integration Time Register

(0x01)

Wait Time Register (0x03)

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