DAC707SH datasheet(13/27 Pages) TI

13 / 27 page

DAC8531

SBAS192B

www.ti.com

FIGURE 5. Output Stage During Power-Down.

POWER-DOWN MODES

The DAC8531 supports four separate modes of operation.

These modes are programmable by setting two bits (PD1

and PD0) in the control register. Table I shows how the state

of the bits corresponds to the mode of operation of the

device.

When both bits are set to 0, the part works normally with its

typical current consumption of 250

µA at 5V. However, for the

three power-down modes, the supply current falls to 200nA

at 5V (50nA at 3V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has

the advantage that the output impedance of the part is known

while the part is in power-down mode. There are three

different options. The output is connected internally to GND

through a 1k

Ω resistor, a 100kΩ resistor, or it is left open-

circuited (High-Z). The output stage is illustrated in Figure 5.

FIGURE 6. DAC8531 to 80C51/80L51 Interface.

FIGURE 7. DAC8531 to Microwire Interface.

MICROPROCESSOR

INTERFACING

DAC8531 TO 8051 INTERFACE

Figure 6 shows a serial interface between the DAC8531 and

a typical 8051-type microcontroller. The setup for the inter-

face is as follows: TXD of the 8051 drives SCLK of the

DAC8531, while RXD drives the serial data line of the part.

The SYNC signal is derived from a bit-programmable pin on

the port. In this case, port line P3.3 is used. When data is to

be transmitted to the DAC8531, P3.3 is taken LOW. The

8051 transmits data only in 8-bit bytes; thus only eight falling

clock edges occur in the transmit cycle. To load data to the

DAC, P3.3 is left LOW after the first eight bits are transmitted

and a second write cycle is initiated to transmit the second

byte of data. P3.3 is taken HIGH following the completion of

the third write cycle. The 8051 outputs the serial data in a

format which has the LSB first. The DAC8531 requires its

data with the MSB as the first bit received. The 8051 transmit

routine must therefore take this into account, and “mirror” the

data as needed.

PD1 (DB17)

PD0 (DB16)

OPERATING MODE

Normal Operation

——

Power-Down Modes

Output 1k

Ω to GND

Output 100k

Ω to GND

High-Z

TABLE I. Modes of Operation for the DAC8531.

All linear circuitry is shut down when the power-down mode

is activated. However, the contents of the DAC register are

unaffected when in power-down. The time to exit

power-down is typically 2.5

µs for V

DD =

5V, and 5

µs

for VDD = 3V. See the Typical Characteristics for more

information.

DAC8531 TO Microwire INTERFACE

Figure 7 shows an interface between the DAC8531 and any

Microwire compatible device. Serial data is shifted out on the

falling edge of the serial clock and is clocked into the

DAC8531 on the rising edge of the SK signal.

Resistor

String DAC

Amplifier

Power-Down

Circuitry

Resistor

Network

OUT

80C51/80L51(1)

P3.3

TXD

RXD

DAC8531(1)

SYNC

SCLK

NOTE: (1) Additional pins omitted for clarity.

SYNC

SCLK

MicrowireTM

DAC8531(1)

NOTE: (1) Additional pins omitted for clarity.

Microwire is a registered trademark of National Semiconductor.

DAC707SH Datasheet(PDF) 13 Page - Texas Instruments

DAC707SH Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL