TSL202R datasheet(3/13 Pages) AMSCO

3 / 13 page

TSL202R

128 y 1 LINEAR SENSOR ARRAY

TAOS032F − JANUARY 2012

E 2012, TAOS Inc.

The LUMENOLOGY

r Company

www.taosinc.com

Terminal Functions

TERMINAL

NAME

NO.

DESCRIPTION

AO1

Analog output of section 1

AO2

Analog output of section 2

CLK

Clock. Clk controls charge transfer, pixel output, and reset.

GND

5,12

Ground (substrate). All voltages are referenced to GND.

7, 9, 11, 14

No internal connection

SI1

Serial input (section 1). SI1 defines the start of the data-out sequence.

SI2

Serial input (section 2). SI2 defines the start of the data-out sequence.

SO1

Serial output (section 1). SO1 provides a signal to drive the SI2 input.

SO2

Serial output (section 2). SO2 provides a signal to drive the SI input of another device for

cascading or as an end-of-data indication.

VDD

Supply voltage. Supply voltage for both analog and digital circuitry.

Detailed Description

The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode

generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During

the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.

The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration

time. The integration time is the interval between two consecutive output periods.

The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle

is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)†. As the SI pulse

is clocked through the 128-bit shift register, the charge on the sampling capacitor of each pixel is sequentially

connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes

low, the pixel integrator is reset. On the 129th clock rising edge, the SI pulse is clocked out of the shift register

and the output assumes a high-impedance state. Note that this 129th clock pulse is required to terminate the

output of the 128th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented

as early as the 130th clock pulse, thereby initiating another pixel output cycle.

The voltage developed at analog output (AO) is given by:

Vout = Vdrk + (Re) (Ee) (tint)

where:

Vout

is the analog output voltage for white condition

Vdrk

is the analog output voltage for dark condition

is the device responsivity for a given wavelength of light given in V/(

μJ/cm2)

is the incident irradiance in

μW/cm2

tint

is integration time in seconds

AO is driven by a source follower that requires an external pulldown resistor (330-

Ω typical). The output is

nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device

is not in the output phase, AO is in a high impedance state.

A 0.1

μF bypass capacitor should be connected between VDD and ground as close as possible to the device.

† For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.

TSL202R Datasheet(PDF) 3 Page - ams AG

TSL202R Datasheet(HTML) 3 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

Datasheet Download

Link URL