Pin Configuration

AT43101 pins are defined by the following two tables. The

Pin Descriptions Table lists and describes the function of

each signal used in the chip set. The Pin Assignment Table

lists the signals connected to each pin for each mode and

the buffer type implemented for the corresponding pin. The

buffer type listed in the Pin Assignment Table does not al-

ways agree with the signal type listed in the Pin Description

Table because the chip implements buffer types that sup-

port both modes of each pin. The pullup resistors included

on chip as shown in the table have a nominal value of

375K ohms. An asterisk, “*”, appended to a signal name

indicates the signal is active low.

AT43101 Logical Pin Descriptions

Name

Type

Description

D[15:0]

Bidir

PCMCIA Data Bus

A[24:0]

Input

PCMCIA Address Bus

CE2*

Input

Active low, PCMCIA byte enable for odd byte

CE1*

Input

Active low, PCMCIA byte enable for even byte

OE*

Input

Active low, PCMCIA output enable signal

WE*

Input

Active low, PCMCIA write enable signal

REG*

Input

PCMCIA signal high for common memory, low for attribute memory

ID[15:0]

Bidir

Memory data bus

IA[24:1]

Output

Memory address bus

SGL/DBL*

Input

Address decoder mode control input per function table

SEL[1:0]

Input

Address decoder selection inputs per function table

B/A*

Input

Mode select input. Low selects mode A, High selects mode B.

DEC[2:0]

Input

Address Inputs decoded to generate ICE[7:0]* outputs

IOEH*

Output

Active low output enable for upper byte of memory

IOEL*

Output

Active low output enable for lower byte of memory

IWEH*

Output

Active low write enable for upper byte of memory

IWEL*

Output

Active low write enable for lower byte of memory

IWP*

Input

Input from write protect switch

WP

Output

Output to PCMCIA write protect signal

ICE[7:0]*

Output

Active low chip enable outputs for 8 pairs of memory devices

Reset

Input

Active high reset

IR*

Output

Output of inverted reset

WPATT

Input

Active high attribute memory protect signal

R/B*

Output

Output from IR/B* and attribute memory Ready/Busy*

IR/B*

Input

Active low Ready/Busy* input for common memory

2

AT43101