SGL/DBL* = H

SGL/DBL* = L

SEL[1:0]

DEC[2:0]

ICE[7:0]*

SEL[1:0]

DEC[2:0]

ICE[7:0]*

XX

LLL

HHHHHHHL

LL

XLL

HHHHHHHL

XX

LLH

HHHHHHLH

LL

XLH

HHHHHHLH

XX

LHL

HHHHHLHH

LL

XHL

HHHHHLHH

XX

LHH

HHHHLHHH

LL

XHH

HHHHLHHH

XX

HLL

HHHLHHHH

XX

HLH

HHLHHHHH

LH

XXX

HHLHHHHH

XX

HHL

HLHHHHHH

HL

XXX

HLHHHHHH

XX

HHH

LHHHHHHH

HH

XXX

LHHHHHHH

Address Decoder Operation

OE*

WE*

CE2*

CE1*

A0

IOEL*

IOEH*

IWEL*

IWEH*

H

H

X

X

X

HHHH

L

H

H

H

X

HHHH

L

H

H

LLL

H

H

H

LH

HL

H

H

L

H

H

LH

LH

X

H

L

H

H

LH

L

L

X

L

L

H

H

H

L

H

H

X

HHHH

HL

HL

L

H

H

L

H

H

L

H

L

HHHH

L

H

L

L

H

X

HHH

L

HL

L

L

X

H

H

L

L

Byte Control Logic Operation

The AT43101 provides separate output and write enables for

the upper and lower bytes of the memory array to implement

byte addressing. The assertion of these outputs under the

control of A0, CE2*, CE1*, OE* and WE* is given by the

following table when REG* is high.

The IWP* input provides write protection for common

memory. When IWP* is low, assertion of IWEL* and

IWEH* is inhibited. The WPATT input provides write pro-

tection for the attribute memory when high. This signal is

pulled down internally for applications not requiring write

protection. In addition, the AT43101 is disabled for 3 milli-

seconds during power up to prevent writes from occurring

to either attribute or common memory. The state of the

A*/B pin is also latched at this time. The AT43101 does

not support the optional PCMCIA WAIT* signal.

AT43101

5