AT48801 datasheet(16/17 Pages) ATMEL

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Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms

(1)

Note:

1. AC Inputs during testing are driven at VCC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing meas-

urements are made at VIH min. for a logic 1 and

VIL max. for a logic 0.

The values in this table are valid for VCC = 5.0V

± 20% and Load Capacitance = 80 pF.

Symbol

Parameter

12 MHz Osc

Variable Oscillator

Units

Min

Max

Min

Max

tXLXL

Serial Port Clock Cycle Time

1.0

12tCLCL

µs

tQVXH

Output Data Setup to Clock Rising Edge

700

10tCLCL - 133

tXHQX

Output Data Hold After Clock Rising Edge

2tCLCL - 33

tXHDX

Input Data Hold After Clock Rising Edge

tXHDV

Clock Rising Edge to Input Data Valid

700

10tCLCL - 133

Serial Port Timing: Shift Register Mode Test Conditions

Float Waveforms

(1)

Note:

1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when a 100 mV change from

the loaded VOH/VOL level occurs.

1-16

AT48801

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