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LT1358/LT1359

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Circuit Operation

The LT1358/LT1359 circuit topology is a true voltage

feedback amplifier that has the slewing behavior of a

current feedback amplifier. The operation of the circuit can

be understood by referring to the simplified schematic.

The inputs are buffered by complementary NPN and PNP

emitter followers which drive a 500

Ω resistor. The input

voltage appears across the resistor generating currents

which are mirrored into the high impedance node. Comple-

mentary followers form an output stage which buffers the

gain node from the load. The bandwidth is set by the input

resistor and the capacitance on the high impedance node.

The slew rate is determined by the current available to

charge the gain node capacitance. This current is the

differential input voltage divided by R1, so the slew rate is

proportional to the input. Highest slew rates are therefore

seen in the lowest gain configurations. For example, a 10V

output step in a gain of 10 has only a 1V input step,

whereas the same output step in unity gain has a 10 times

greater input step. The curve of Slew Rate vs Input Level

illustrates this relationship. The LT1358/LT1359 are tested

for slew rate in a gain of –2 so higher slew rates can be

expected in gains of 1 and –1, and lower slew rates in

higher gain configurations.

The RC network across the output stage is bootstrapped

when the amplifier is driving a light or moderate load and

has no effect under normal operation. When driving a

capacitive load (or a low value resistive load) the network

is incompletely bootstrapped and adds to the compensa-

tion at the high impedance node. The added capacitance

slows down the amplifier which improves the phase

margin by moving the unity-gain frequency away from the

pole formed by the output impedance and the capacitive

load. The zero created by the RC combination adds phase

to ensure that even for very large load capacitances, the

total phase lag can never exceed 180 degrees (zero phase

margin) and the amplifier remains stable.

Power Dissipation

The LT1358/LT1359 combine high speed and large output

drive in small packages. Because of the wide supply

voltage range, it is possible to exceed the maximum

junction temperature under certain conditions. Maximum

junction temperature (TJ) is calculated from the ambient

temperature (TA) and power dissipation (PD) as follows:

LT1358N8: TJ = TA + (PD x 130°C/W)

LT1358S8: TJ = TA + (PD x 190°C/W)

LT1359N:

TJ = TA + (PD x 110°C/W)

LT1359S:

TJ = TA + (PD x 150°C/W)

LT1359S14: TJ = TA + (PD x 160°C/W)

Worst case power dissipation occurs at the maximum

supply current and when the output voltage is at 1/2 of

either supply voltage (or the maximum swing if less than

1/2 supply voltage). For each amplifier PDMAX is:

PDMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL

Example: LT1358 in S8 at 70

°C, VS = ±15V, RL = 500Ω

PDMAX = (30V)(2.9mA) + (7.5V)2/500Ω = 200mW

TJMAX = 70°C + (2 x 200mW)(190°C/W) = 146°C

APPLICATIO S I FOR ATIO

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