ADS901 datasheet(4/13 Pages) TI

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ADS901

SBAS054A

5 Clock Cycles

Data Invalid

CONV

N–5N–4N–3N–2N–1

N+1

N+2

Data Out

Clock

Analog In

N+1

N+2

N+3

N+4

N+5

N+6

N+7

TOP VIEW

SSOP

PIN CONFIGURATION

DESIGNATOR

DESCRIPTION

1+VS

Analog Supply

2LVDD

Output Logic Driver Supply Voltage

Bit 10

Data Bit 10 (D0) (LSB)

Bit 9

Data Bit 9 (D1)

Bit 8

Data Bit 8 (D2)

Bit 7

Data Bit 7 (D3)

Bit 6

Data Bit 6 (D4)

Bit 5

Data Bit 5 (D5)

Bit 4

Data Bit 4 (D6)

Bit 3

Data Bit 3 (D7)

Bit 2

Data Bit 2 (D8)

Bit 1

Data Bit 1 (D9) (MSB)

GND

Analog Ground

GND

Analog Ground

CLK

Convert Clock Input

Output Enable, Active Low

Pwrdn

Power Down Pin

+VS

Analog Supply

GND

Analog Ground

GND

Analog Ground

LpBy

Positive Ladder Bypass

REFT

Top Reference Input

No Connection

REFB

Bottom Reference Input

LnBy

Negative Ladder Bypass

Common-Mode Voltage Output

Analog Input

+VS

Analog Supply

PIN DESCRIPTIONS

TIMING DIAGRAM

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tCONV

Convert Clock Period

100

µsns

Clock Pulse Low

Clock Pulse High

Aperture Delay

Data Hold Time, CL = 0pF

3.9

New Data Delay Time, CL = 15pF max

(LSB) Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

(MSB) Bit 1

GND

LnBy

REFB

REFT

LpBy

GND

Pwrdn

CLK

ADS901

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